HDLBits FSM/Fsm3s

HDLBits FSM/Fsm3s

 See also: State transition logic for this FSM

The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous reset that resets the FSM to state A. (This is the same problem as Fsm3 but with a synchronous reset.)

State	Next state		Output
	in=0	in=1
A	A	B	0
B	C	B	0
C	A	D	0
D	C	B	1

module top_module(
    input clk,
    input in,
    input reset,
    output out); //
    
    parameter A=2'd0,B=2'd1,C=2'd2,D=2'd3; 
    reg [1:0] state; // Make sure state and next are big enough to hold the state encodings.
    reg [1:0] next;
    
    // This is a sequential always block
    //非同步 :reset , clk 二者獨立
    //同步 :  僅能依賴 clk  
   // 非同步 always @(posedge clk, posedge areset) begin
   // 同步   always @(posedge clk, posedge reset) begin
    always @(posedge clk) begin
  if (reset) state <= A;
        else state <= next;
end
 // State transition logic
    always@(*) begin
case (state)
A: next = in ? B : A;
B: next = in ? B : C;
C: next = in ? D : A;
D: next = in ? B : C;
endcase
    end
    // Output logic
    // assign out = (state == ...);
    always@(*) begin
   case (state)
A: out = 1'b0;
B: out = 1'b0;
C: out = 1'b0;
D: out = 1'b1;
       endcase
    end  
endmodule