HDLBits Simple FSM2S

HDLBits Simple FSM2S

 This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.

This exercise is the same as fsm2, but using synchronous reset.

同步

    always @(posedge clk) begin

 非同步

 always @(posedge clk, posedge areset) begin   

module top_module(
    input clk,
    input reset,    // Synchronous reset to OFF
    input j,
    input k,
    output out); //  
    parameter OFF=0, ON=1; 
    reg state, next_state;
    
    always @(posedge clk) begin
        // State flip-flops with asynchronous reset
        if(reset) state<=OFF;
        else state<=next_state;
    end
    
    always @(*) begin
        case(state)
            OFF: next_state=j?ON:OFF;
            ON:  next_state=k?OFF:ON;
        endcase
    end
    // Output logic
    // assign out = (state == ...);
    always@(*) begin
   case (state)
OFF: out = 1'b0;
ON: out = 1'b1;
endcase
    end  
endmodule