HBLbits_Verilog Karnaugh Map

 HBLbits_Verilog Karnaugh Map

 Karnaugh Map to Circuit

·        3-variable

·        4-variable

·        4-variable

·        4-variable

·        Minimum SOP and POS

·        Karnaugh map

·        Karnaugh map

·        K-map implemented with a multiplexer

 

Kmap1

module top_module(     input a,     input b,     input c,     output out  );     assign out= ~  (~a & ~b & ~c) ; endmodule

Kmap2

y = B'C' + A'D' + BCD + AB'D

module top_module(     input a,     input b,     input c,     input d,     output out  );     assign out = (~b & ~c) | (~a & ~d) | ( b & c & d) | (a & ~b & d); endmodule

Kmap3

 

y = A + B'C

module top_module(     input a,     input b,     input c,     input d,     output out  );     assign out= a | (~b&c); endmodule

 Kmap4

module top_module(     input a,     input b,     input c,     input d,     output out  );     //out = sigma(1,2,4,7,8,11,13,14);     assign out = (~a & ~b & ~c & d) | (~a & ~b & c & ~d) |  (~a &  b & ~c & ~d) | (~a &  b & c &  d) |         (a & ~b & ~c & ~d) | ( a & ~b & c &  d) |  ( a &  b & ~c &  d) | ( a &  b & c &  ~d) ; endmodule

Exams/ece241 2013 q2

A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively.

module top_module (     input a,     input b,     input c,     input d,     output out_sop,     output out_pos );         assign out_sop = (~a & ~b & c) | (c & d);      assign out_pos = (c) & (~b | d) & (~a | d); endmodule

Exams/m2014 q3

Consider the function f shown in the Karnaugh map below.

f(x1, x2, x3, x4) = (x2 + x3)(x3 + x4)(x1' + x3')

assign f = (x2 | x3) & (x3 | x4) & (~x1 | ~x3);

f(x1, x2, x3, x4) = x1'x3 + x1x2x3'

assign f = (~x1 & x3) | (x1 & x2 & ~x3);

module top_module (     input [4:1] x,     output f );     assign f = (x[2] | x[3]) & (x[3] | x[4]) & (~x[1] | ~x[3]); endmodule

 

Exams/ece241 2014 q3

For the following Karnaugh map, give the circuit implementation using one 4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using as few as possible. You are not allowed to use any other logic gate and you must use a and b as the multiplexer selector inputs, as shown on the 4-to-1 multiplexer below.

You are implementing just the portion labelled top_module, such that the entire circuit (including the 4-to-1 mux) implements the K-map.

mux_in (a, b, c, d) = a'b'd + ab'd' + abcd + a'b'c

assign mux_in = (~a & ~b & d) | (a & ~b & ~d) | (a & b & c & d) | (~a & ~b & c);

module top_module (     input c,     input d,     output [3:0] mux_in );     assign mux_in = (c==0&d==0)?4'b0100:(c==0&d==1)?4'b0001:(c==1&d==0)?4'b0101:4'b1001; endmodule

 

module top_module (         input c,         input d,         output [3:0] mux_in );                 // After knowing how to split the truth table into four columns,         // the rest of this question involves implementing logic functions         // using only multiplexers (no other gates).         // I will use the conditional operator for each 2-to-1 mux: (s ? a : b)         assign mux_in[0] = (c ? 1 : (d ? 1 : 0));   // 2 muxes: c|d         assign mux_in[1] = 0;                                             // No muxes:  0         assign mux_in[2] = d ? 0 : 1;                          // 1 mux:    ~d         assign mux_in[3] = c ? (d ? 1 : 0) : 0;             // 2 muxes: c&d         endmodule