HBLbits_Verilog Basic_Fsm hdlc

HBLbits_Verilog Basic_Fsm hdlc

Synchronous HDLC framing involves decoding a continuous bit stream of data to look for bit patterns that indicate the beginning and end of frames (packets). Seeing exactly 6 consecutive 1s (i.e., 01111110) is a "flag" that indicate frame boundaries. To avoid the data stream from accidentally containing "flags", the sender inserts a zero after every 5 consecutive 1s which the receiver must detect and discard. We also need to signal an error if there are 7 or more consecutive 1s.
Create a finite state machine to recognize these three sequences:

• 0111110: Signal a bit needs to be discarded (disc).

• 01111110: Flag the beginning/end of a frame (flag).

• 01111111...: Error (7 or more 1s) (err).

When the FSM is reset, it should be in a state that behaves as though the previous input were 0.
Here are some example sequences that illustrate the desired operation.

High-Level Data Link Control (HDLC) is a bit-oriented code-transparent synchronous data link layer protocol developed by the International Organization for Standardization (ISO). The standard for HDLC is ISO/IEC 13239:2002.

HDLC provides both connection-oriented and connectionless service.

HDLC can be used for point-to-multipoint connections via the original master-slave modes Normal Response Mode (NRM) and Asynchronous Response Mode (ARM), but they are now rarely used; it is now used almost exclusively to connect one device to another, using Asynchronous Balanced Mode (ABM).

module top_module(
    input clk,
    input reset,    // Synchronous reset
    input in,
    output disc,
    output flag,
    output err);
    
    parameter none=4'd0,one=4'd1,two=4'd2,three=4'd3,four=4'd4;
    parameter five=4'd5,six=4'd6,error=4'd7,discard=4'd8,flags=4'd9;
    
    reg[3:0] state,next_state;
    
    always @(posedge clk) begin
        if(reset)begin
            state <= none;
        end
        else begin
            state <= next_state;
        end
    end
    
    always@(*)begin
        case(state)
            none:begin
                next_state = in?one:none;
            end
            one:begin
                next_state = in?two:none;
            end
            two:begin
                next_state = in?three:none;
            end
            three:begin
                next_state = in?four:none;
            end   
            four:begin
                next_state = in?five:none;
            end
            five:begin
                next_state = in?six:discard;
            end       
            six:begin
                next_state = in?error:flags;
            end                
            error:begin
                next_state = in?error:none;
            end        
            discard:begin
                next_state = in?one:none;
            end 
            flags:begin
                next_state = in?one:none;
            end 
        endcase
    end
            
always@(*)begin
        disc = (state==discard);
        flag = (state==flags);
        err  = (state==error);
end        
            
endmodule