alex9ufo 聰明人求知心切: HBLbits_Verilog Basic

2021年5月5日星期三

HBLbits_Verilog Basic_Exams/review2015 count1k

Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is synchronous, and should reset the counter to 0.

module top_module (
input clk,
input reset,
output [9:0] q);
always @(posedge clk) begin
if (reset)
q=0;
else
begin
if ( q==999)
q=0;
else
q=q+1;
end
end
endmodule

alex9ufo 聰明人求知心切

2021年5月5日星期三

HBLbits_Verilog Basic_Exams/review2015 count1k

module top_module (
input clk,
input reset,
output [9:0] q);
always @(posedge clk) begin
if (reset)
q=0;
else
begin
if ( q==999)
q=0;
else
q=q+1;
end
end
endmodule

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WOKWI ESP32 LED Control , Node-Red MQTT SQLITE

2021年5月5日 星期三

HBLbits_Verilog Basic_Exams/review2015 count1k

module top_module ( input clk, input reset, output [9:0] q); always @(posedge clk) begin if (reset) q=0; else begin if ( q==999) q=0; else q=q+1; end endendmodule

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WOKWI ESP32 LED Control , Node-Red MQTT SQLITE

2021年5月5日星期三

module top_module (
input clk,
input reset,
output [9:0] q);
always @(posedge clk) begin
if (reset)
q=0;
else
begin
if ( q==999)
q=0;
else
q=q+1;
end
end
endmodule

WOKWI ESP32 LED Control , Node-Red MQTT SQLITE 　