DE2-115 Verilog code for 4:1 Multiplexer (MUX)

 DE2-115 Verilog code for 4:1 Multiplexer (MUX)

//Mux 

module mux2_de2( SW,LEDR );

input [17:0] SW;

output [17:0] LEDR;

mux2(SW[17:16],SW[3:0],LEDR[0]);

endmodule

//======================

module mux2( select, d, q );

input[1:0] select;

input[3:0] d;

output q;

reg q;

wire[1:0] select;

wire[3:0] d;

always @(d or select)

q = d[select];

endmodule

DE2-115 Pin assigment

https://www.mediafire.com/file/1c3we0lftdz3qaq/DE2_115_pin_assignments.csv/file

Examples verilog.v

https://www.mediafire.com/file/kngm038siz036kj/ex1.rar/file