Verilog Not , Buffer , Buffer if 0 , Buffer if 1 , Not if 0 , Not if 1

Verilog  Not , Buffer , Buffer if 0 , Buffer if 1 , Not if 0 , Not if 1

參考 http://www.asic-world.com/verilog/gate1.html

Transmission Gate Primitives
Transmission gates are bi-directional and can be resistive or non-resistive.
Syntax: keyword unique_name (inout1, inout2, control);
Gate Description not N-output inverter buf N-output buffer. bufif0 Tri-state buffer, Active low en. bufif1 Tri-state buffer, Active high en. notif0 Tristate inverter, Low en. notif1 Tristate inverter, High en.
Transmission gates tran and rtran are permanently on and do not have a control line. Tran can be used to interface two wires with seperate drives, and rtran can be used to weaken signals.

//=============================================
//gate level basic gate buffer not bufif0 bufif1
//=============================================
module buf_not(
O_buf_1 ,O_buf_2,I,
O_not , X,
O_bufif1_1, C,
O_bufif0_1,
O_notif1,  Y,
O_notif0_1, Z
);
input I,C,X,Y,Z;
output O_buf_1,O_buf_2,O_not,O_bufif1_1,O_bufif0_1,O_notif1,O_notif0_1;

buf    (O_buf_1 ,O_buf_2,I);
not N1 (O_not , X);
bufif1 (O_bufif1_1,I,C); //buf_if_1  C=control pin
bufif0 (O_bufif0_1, I, X);             //buf_if_1  X=control pin
notif1 N2 (O_notif1, I, Y); //buf_if_1  Y=control pin
notif0 (O_notif0_1,I, Z); //buf_if_1  Z=control pin

endmodule

//========================================

// Ch04 T.V
// basic gate  buffer, not, bufferif0 ,bufferif1 (測試平台程式)

// 時間單位 1ns, 時間精確度1 ps
`timescale 100ns/10ps

module T;
//input
reg  I=1'b0; //暫存器資料初值為‘0’
reg  X=1'b0;
reg  C=1'b0;
reg  Y=1'b0;
reg  Z=1'b0;

//output
wire O_buf_1,O_buf_2,O_not,O_bufif1_1,O_bufif0_1,O_notif1,O_notif0_1 ;


// 建立and_gate 的模組例證
buf_not UUT(
.O_buf_1(O_buf_1) ,.O_buf_2 (O_buf_2),.I(I),
.O_not(O_not) , .X(X),
.O_bufif1_1(O_bufif1_1),.C(C),
.O_bufif0_1(O_bufif0_1),
.O_notif1(O_notif1), .Y(Y),
.O_notif0_1(O_notif0_1),.Z(Z)
);


// initial程序結構區塊, 產生A、B輸入信號波形
initial
begin
  #100; // 100ns
I=1'b1;  //test Buf , NOT gate
X=1'b1;
C=1'b1;
  #100; // 200ns
    C=1'b0; //buffer if 1 
   
  #100; // 300ns
X=1'b0; //buffer if 0 
C=1'b1; //buffer if 1

  #100; // 400ns
X=1'b1; //buffer if 0 
C=1'b1; //buffer if 1
  #100; // 500ns
  Y=1'b1; //buffer if 0 
Z=1'b1; //buffer if 1
  #100;    // 600ns
    I=1'b0;
    Y=1'b1; //buffer if 0 
Z=1'b1; //buffer if 1 
  #100; // 700ns
$stop;

  end


endmodule

//========================================