8bit x 8bits 乘法器轉BCD顯示於七段顯示器--適用於DE2-70

module _8x8bit_mul_BCD_7seg(SW,LEDR,HEX0 ,HEX1 ,HEX2,HEX3,,HEX4,HEX5,HEX6,HEX7);
input [15:0]SW;
output [15:0]LEDR;
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; //7-segment display

 wire [7:0] a0,b0;

 wire [3:0] S4,S3,S2,S1,S0;
 wire [7:0] segout0;   //HEX 0
 wire [7:0] segout1;   //HEX 1
 wire [7:0] segout2;   //HEX 2
 wire [7:0] segout3;   //HEX 3
 wire [7:0] segout4;   //HEX 4

 wire [15:0] Product;

 assign a0=SW[7:0];
 assign b0=SW[15:8];

 assign LEDR[15:0]=Product;

 mult8S U0(Product,a0,b0);
 BIN2BCD(Product,S4,S3,S2,S1,S0);

 //Display BCD Sum to 7-segment Display

    _7seg UUT0(.hex(S0),.seg(segout0));
    _7seg UUT1(.hex(S1),.seg(segout1));
    _7seg UUT2(.hex(S2),.seg(segout2));
    _7seg UUT3(.hex(S3),.seg(segout3));
    _7seg UUT4(.hex(S4),.seg(segout4));
           
 assign HEX0=segout0[6:0];
 assign HEX1=segout1[6:0];
 assign HEX2=segout2[6:0];
 assign HEX3=segout3[6:0];
 assign HEX4=segout4[6:0];


 assign HEX5=7'h7f; //Blank 7-segment 
 assign HEX6=7'h7f;
 assign HEX7=7'h7f;   //set 1 => off LED



endmodule


// ------------------------------------------------------------------------
//8-bit multiplier
//Filename : mult16S.v : P = A * B 
//-------------------------------------------------------------------------
module mult8S(P,A,B);
output [15:0]P; // 32-bit product

input [7:0]A; //Multiplicand
input [7:0]B; //Multiplier

reg [15:0] p;
reg [15:0] temp;
reg [7:0] a;
reg [7:0] b;
integer  i;

always @(A or B)
   begin
a = A;
b = B;
if (a==0 || b==0) // q=0 when a or b equal 0
p = 15'b0;        
else if (a==1) // q=b when a equal 1
p = {8'b0000_0000,b};
else if (b==1) // q=a when b equal 1
p = {8'b0000_0000,a};
else 
begin
p = 15'b0;
for (i=0; i<8; i=i+1)
if  (b[i] == 1)
begin
                     temp = a << i; // shift left N bits
                     p = p + temp; 
end
end
    end
assign P = p;


endmodule



module BIN2BCD(Binary,ten_thous,thousands,hundreds,tens,ones);

input [15:0]Binary;

output ten_thous;
output thousands;
output hundreds;
output tens;
output ones;

reg [3:0]ten_thous;
reg [3:0]thousands;
reg [3:0]hundreds;
reg [3:0]tens;
reg [3:0]ones;


integer i;


always@(Binary)
begin 
 ten_thous=4'd0;
 thousands=4'd0;
 hundreds=4'd0;
 tens=4'd0;
 ones=4'd0;


 for (i=15; i>=0; i=i-1)
 begin
 //add 3 to column >=5 ;
 if (ten_thous>=5)
    ten_thous=ten_thous+3;
    
 if (thousands>=5)
    thousands=thousands+3;
    
 if (hundreds>=5)
    hundreds=hundreds+3;
    
 if (tens>=5)
    tens = tens + 3;
   
 if (ones>=5)
    ones = ones +3;   
   
 //shift left one bit
 ten_thous=ten_thous<<1;
 ten_thous[0]=thousands[3];

 thousands=thousands<<1;
 thousands[0]=hundreds[3];

 hundreds=hundreds<<1;
 hundreds[0]=tens[3];
  
 tens=tens<<1;
 tens[0]=ones[3];

 ones=ones<<1;
 ones[0]=Binary[i];

 end


 end

endmodule


//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//----------------------------------------- 
module _7seg(hex , seg);
    input  [3:0] hex;
    output [7:0] seg;
    reg    [7:0] seg;
 // segment encoding
 //      0
 //     ---  
 //  5 |   | 1
 //     ---   <- 6
 //  4 |   | 2
 //     ---
 //      3
 always @(hex)
 begin
  case (hex)
       // Dot point is always disable
       4'b0001 : seg = 8'b11111001;   //1 = F9H
       4'b0010 : seg = 8'b10100100;   //2 = A4H
       4'b0011 : seg = 8'b10110000;   //3 = B0H
       4'b0100 : seg = 8'b10011001;   //4 = 99H
       4'b0101 : seg = 8'b10010010;   //5 = 92H
       4'b0110 : seg = 8'b10000010;   //6 = 82H
       4'b0111 : seg = 8'b11111000;   //7 = F8H
       4'b1000 : seg = 8'b10000000;   //8 = 80H
       4'b1001 : seg = 8'b10010000;   //9 = 90H
       4'b1010 : seg = 8'b10001000;   //A = 88H
       4'b1011 : seg = 8'b10000011;   //b = 83H
       4'b1100 : seg = 8'b11000110;   //C = C6H
       4'b1101 : seg = 8'b10100001;   //d = A1H
       4'b1110 : seg = 8'b10000110;   //E = 86H
       4'b1111 : seg = 8'b10001110;   //F = 8EH
       default : seg = 8'b11000000;   //0 = C0H
     endcase
   end
   
endmodule