P6-83 16x8 bits 1 Port RAM (16x8 =128bits) 適用於DE2-70

P6-83 16bits  1 Port RAM 適用於DE2-70

因為Clock 50MHz 太快了 所以將Clock 速度Down 下來

assign ADDR = SW[3:0] ;  //1'st port address 

assign Din=SW[15:8];      //Data input 

assign we=SW[17];

  assign LEDG[7:0] = Dout; //1'st data output 

動作順序 (1) Setting Address SW[3:0] 

                  (2) Setting Data  SW[15:8]

                  (3) Setting Writing Enable SW[17]

                  (4) 等

if (!key_delay0[3] && key_delay0[2] && we )  

//Filename : RAM16x8_1Port

module RAM16x8_1Port (LEDG, LEDR, CLOCK_50, KEY , SW);

output [7:0] LEDG;

output [17:0] LEDR;

input  CLOCK_50 ;

input  [3:0] KEY;

input  [17:0] SW;

//(clk, we, ADDR, DPR_ADDR, di, SP_OUT, DP_OUT);

parameter DATA_WDTH = 8, ADDR_WDTH = 4;

wire we; //Write Enable

wire [ADDR_WDTH-1:0] ADDR;     //1'st port address  

wire [DATA_WDTH-1:0] Din;       //Data input

reg  [DATA_WDTH-1:0] Dout;       //Data output

  

// 16-byte ram 

reg    [DATA_WDTH-1:0] ram [15:0];  //16x8 Bits ,Address bus= 2^4 ,4bits

reg    [ADDR_WDTH-1:0] read_ADDR;     //Address for Read

          //Data bits =8

          

          

          

reg [3:0] key_delay0;    //For Clock Down to 26bits 

reg [27:0] Counter_inc ;

assign ADDR = SW[3:0] ;  //1'st port address 

assign Din=SW[15:8];      //Data input 

assign we=SW[17];

always @ (posedge CLOCK_50 ) begin

if (!key_delay0[3] && key_delay0[2] && we ) //KEY[0] = Counter_inc[25]

ram[ADDR] <= Din; 

 

  read_ADDR <= ADDR; 

 

Dout = ram[read_ADDR]; 

key_delay0 <= { key_delay0[2:0],Counter_inc[25]};   //delay for KEY[0]

Counter_inc = Counter_inc + 28'b1;

  end

assign LEDG[7:0] = Dout; //1'st data output 

endmodule