P6-52 以for迴圈設計4bit Shift Left REG

P6-52 以for迴圈設計4bit Shift Left REG 

 
assign RESET = KEY[0];   //Reset 

assign Din0 = SW[0];          //Data Input



// Filename : _4bit_Shift_REG

module _4bit_Shift_REG (LEDG, LEDR, CLOCK_50, KEY , SW);
parameter Length =4;
output [7:0] LEDG;
output [17:0] LEDR;
input  CLOCK_50 ;
input  [3:0] KEY;
input  [17:0] SW;

wire RESET , Din0 ;
integer i;
reg [3:0 ] Qout;

reg [3:0] key_delay0;

reg [27:0] Counter_inc ;

assign RESET = KEY[0];
assign Din0 = SW[0];


assign LEDR[3:0] = Qout;

    
always @ (posedge CLOCK_50 )
begin
//Positive edge CLK and asynchronous RESET
if (!RESET)

Qout = 4'b0000;
else if (!key_delay0[3] && key_delay0[2]) //KEY[0] = Counter_inc[27]
begin

for (i=Length-1; i>0; i = i-1)
Qout[i] = Qout[i-1];
Qout[0] = Din0;
end

key_delay0 <= { key_delay0[2:0],Counter_inc[25]};   //delay for KEY[0]

Counter_inc = Counter_inc + 28'b1;

 end

endmodule

/*
//----------------------------------------
//4-bit shift left register using for loop
//filename : shl4_for.v
//----------------------------------------
module shl4_for(Q, CLK, RESET, Din);
parameter length = 4;
output [length-1:0] Q;
input CLK, RESET;
input Din;
integer i;
reg [3:0] Q;

always @ (posedge CLK)
 begin 
  if (RESET)
    Q = 4'b0000;
  else
   begin
    for (i=length-1; i>0; i = i-1)
      Q[i] = Q[i-1];
    Q[0] = Din;
   end
 end
endmodule
*/