P6-10 Blocking assignment 4-bit Register

P6-10 Blocking assignment 4-bit Register 適用於DE2-70
//Clock ==> KEY[1]
//Reset ==> KEY[0]
//Data  ==> SW[0]
//

module Reg_bpa(CLOCK_50,SW, KEY, LEDR, LEDG );

input  [17:0] SW; // toggle switches
input  [7:0]  KEY;
input  CLOCK_50;    //Clock 50MHZ
output [17:0] LEDR; // red LEDs
output [7:0]  LEDG; // green LEDs


    /*
output [3:0] Qout;
input CLK, RESET;
input Din;
*/
//wire [3:0] Qout  disable , reg[3:0]Qout;
wire  CLK;
wire  RESET;
wire  KEY1;
reg [3:0] Qout;

//assign to DE2-70 hardware    

    assign CLK = KEY[1];
    assign RESET = KEY[0];
    assign Din =SW[0];
   
   
always @ (negedge CLK or negedge RESET)
//Positive edge CLK and asynchronous RESET
if (!RESET)
Qout = 4'b0000;
else
begin
Qout[0] = Din;
Qout[1] = Qout[0];
Qout[2] = Qout[1];
Qout[3] = Qout[2];
end

assign LEDG[3:0]=Qout;

endmodule




/*
//--------------------------------------------------
//4-bit register for Blocking Procedural Assignment
//Filename : reg_bpa.v
//--------------------------------------------------
module reg4_bpa(Qout, CLK, RESET, Din);
output [3:0] Qout;
input CLK, RESET;
input Din;

reg [3:0] Qout;


always @ (posedge CLK or posedge RESET)
//Positive edge CLK and asynchronous RESET
 if (RESET)
   Qout = 4'b0000;
 else
  begin
   Qout[0] = Din;
   Qout[1] = Qout[0];
   Qout[2] = Qout[1];
   Qout[3] = Qout[2];
  end
endmodule
*/