Digital Logic & Design

源自於
http://www.zeepedia.com/read.php?an_overview_number_systems_digital_logic_design&b=9&c=1

Table of Contents: 

1. AN OVERVIEW & NUMBER SYSTEMS
2. Binary to Decimal to Binary conversion, Binary Arithmetic, 1’s & 2’s complement
3. Range of Numbers and Overflow, Floating-Point, Hexadecimal Numbers
4. Octal Numbers, Octal to Binary Decimal to Octal Conversion
5. LOGIC GATES: AND Gate, OR Gate, NOT Gate, NAND Gate
6. AND OR NAND XOR XNOR Gate Implementation and Applications
7. DC Supply Voltage, TTL Logic Levels, Noise Margin, Power Dissipation
8. Boolean Addition, Multiplication, Commutative Law, Associative Law, Distributive Law, Demorgan’s Theorems
9. Simplification of Boolean Expression, Standard POS form, Minterms and Maxterms
10. KARNAUGH MAP, Mapping a non-standard SOP Expression
11. Converting between POS and SOP using the K-map
12. COMPARATOR: Quine-McCluskey Simplification Method
13. ODD-PRIME NUMBER DETECTOR, Combinational Circuit Implementation
14. IMPLEMENTATION OF AN ODD-PARITY GENERATOR CIRCUIT
15. BCD ADDER: 2-digit BCD Adder, A 4-bit Adder Subtracter Unit
16. 16-BIT ALU, MSI 4-bit Comparator, Decoders
17. BCD to 7-Segment Decoder, Decimal-to-BCD Encoder
18. 2-INPUT 4-BIT MULTIPLEXER, 8, 16-Input Multiplexer, Logic Function Generator
19. Applications of Demultiplexer, PROM, PLA, PAL, GAL
20. OLMC Combinational Mode, Tri-State Buffers, The GAL16V8, Introduction to ABEL
21. OLMC for GAL16V8, Tri-state Buffer and OLMC output pin
22. Implementation of Quad MUX, Latches and Flip-Flops
23. APPLICATION OF S-R LATCH, Edge-Triggered D Flip-Flop, J-K Flip-flop
24. Data Storage using D-flip-flop, Synchronizing Asynchronous inputs using D flip-flop
25. Dual Positive-Edge triggered D flip-flop, J-K flip-flop, Master-Slave Flip-Flops
26. THE 555 TIMER: Race Conditions, Asynchronous, Ripple Counters
27. Down Counter with truncated sequence, 4-bit Synchronous Decade Counter
28. Mod-n Synchronous Counter, Cascading Counters, Up-Down Counter
29. Integrated Circuit Up Down Decade Counter Design and Applications
30. DIGITAL CLOCK: Clocked Synchronous State Machines
31. NEXT-STATE TABLE: Flip-flop Transition Table, Karnaugh Maps
32. D FLIP-FLOP BASED IMPLEMENTATION
33. Moore Machine State Diagram, Mealy Machine State Diagram, Karnaugh Maps
34. SHIFT REGISTERS: Serial In/Shift Left,Right/Serial Out Operation
35. APPLICATIONS OF SHIFT REGISTERS: Serial-to-Parallel Converter
36. Elevator Control System: Elevator State Diagram, State Table, Input and Output Signals, Input Latches
37. Traffic Signal Control System: Switching of Traffic Lights, Inputs and Outputs, State Machine
38. Traffic Signal Control System: EQUATION DEFINITION
39. Memory Organization, Capacity, Density, Signals and Basic Operations, Read, Write, Address, data Signals
40. Memory Read, Write Cycle, Synchronous Burst SRAM, Dynamic RAM
41. Burst, Distributed Refresh, Types of DRAMs, ROM Read-Only Memory, Mask ROM
42. First In-First Out (FIFO) Memory
43. LAST IN-FIRST OUT (LIFO) MEMORY
44. THE LOGIC BLOCK: Analogue to Digital Conversion, Logic Element, Look-Up Table
45. SUCCESSIVE –APPROXIMATION ANALOGUE TO DIGITAL CONVERTER