//KEY[0] PIN_G26 ==> CLK
//KEY[1] PIN_N23 ==> RES
//KEY[2] PIN_P23
//SW[0] PIN_N25 ==> Din
// LEDG[0] PIN_AE22 ==> Qout[0]
// LEDG[1] PIN_AF22 ==> Qout[1]
// LEDG[2] PIN_W19 ==> Qout[2]
// LEDG[3] PIN_V18 ==> Qout[3]
//--------------------------------------------------
//4-bit register for Non-blocking Procedural Assignment
//Filename : reg_nbp.v
//--------------------------------------------------
module reg4_nbp(Qout, CLK, RESET, Din);
output [3:0] Qout;
input CLK, RESET;
input Din;
reg [3:0] Qout;
always @ (posedge CLK or negedge RESET)
//Positive edge CLK and asynchronous RESET
if (!RESET)
Qout <= 4'b0000;
else
begin
Qout[0] <= Din;
Qout[1] <= Qout[0];
Qout[2] <= Qout[1];
Qout[3] <= Qout[2];
end
endmodule
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