HDLBits/Building Larger Circuits/The complete timer（Exams/review2015 fancytimer）
This is the fifth component in a series of five exercises that builds a complex counter out of several smaller circuits. You may wish to do the four previous exercises first (counter, sequence recognizer FSM, FSM delay, and combined FSM).
We want to create a timer with one input that:
- is started when a particular input pattern (1101) is detected,
- shifts in 4 more bits to determine the duration to delay,
- waits for the counters to finish counting, and
- notifies the user and waits for the user to acknowledge the timer.
The serial data is available on the data input pin. When the pattern 1101 is received, the circuit must then shift in the next 4 bits, most-significant-bit first. These 4 bits determine the duration of the timer delay. I'll refer to this as the delay[3:0].
After that, the state machine asserts its counting output to indicate it is counting. The state machine must count for exactly (delay[3:0] + 1) * 1000 clock cycles. e.g., delay=0 means count 1000 cycles, and delay=5 means count 6000 cycles. Also output the current remaining time. This should be equal to delay for 1000 cycles, then delay-1 for 1000 cycles, and so on until it is 0 for 1000 cycles. When the circuit isn't counting, the count[3:0] output is don't-care (whatever value is convenient for you to implement).
At that point, the circuit must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).
The circuit should reset into a state where it begins searching for the input sequence 1101.
Here is an example of the expected inputs and outputs. The 'x' states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once the 1101 and delay[3:0] have been read, the circuit no longer looks at the data input until it resumes searching after everything else is done. In this example, the circuit counts for 2000 clock cycles because the delay[3:0] value was 4'b0001. The last few cycles starts another count with delay[3:0] = 4'b1110, which will count for 15000 cycles.
計時器：①當檢測到特定模式（1101）時啟動；②再移4位以確定延遲時間；③等待計數器完成計數，然後通知用戶並等待用戶確認計時器。
當接收到模式1101時，狀態機必須在4個時鐘周期內輸出shift_ena。此後，狀態機聲明其計數輸出以指示其正在等待計數器，並等待直到輸入done_counting為hi。
data在data輸入引腳上可用。當接收到模式1101時，電路必須隨後移入接下來的4位，即最高有效位在前。這4位確定定時器延遲的持續時間。將其稱為delay [3：0]。
此後，狀態機聲明其計數輸出以指示其正在計數。狀態機必須精確計數（delay [3：0] + 1）* 1000個時鐘周期。例如，delay = 0表示計數1000個周期，而delay = 5表示計數6000個周期。同時輸出當前剩余時間。這應該等於1000個周期的延遲，然後等於1000個周期的delay-1，依此類推，直到1000個周期為0。當電路不計數時，count [3：0]輸出無關緊要。此時，電路完成，以通知用戶計時器已超時，並等待直到輸入ack為1才reset，以查找下一次出現的啟動序列（1101）。電路應重置為開始搜索輸入序列1101的狀態。
這是預期輸入和輸出的示例。“ x”狀態可能會使閱讀有些混亂，它們表明FSM在該周期中不應關心該特定輸入信號。例如，一旦讀取了1101和delay [3：0]，電路將不再查看數據輸入，直到在完成所有其他操作後恢覆搜索為止。在此示例中，電路的計數為2000個時鐘周期，因為delay [3：0]值為4'b0001。最後幾個周期以delay [3：0] = 4'b1110開始另一個計數，該計數將計數15000個周期。
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output [3:0] count,//輸出當前剩余時間
output counting,
output done,
input ack );//與上一題目相比，shift_ena不需要輸出！
parameter S = 0, S1 = 1, S2 = 2, S3 = 3, B0 = 4, B1 = 5, B2 = 6, B3 = 7, COUNT = 8, WAIT = 9;
reg[3:0] state, next_state;
reg[3:0] delay;
reg[13:0] cnt_delay;//根據這個保持counting為1
wire done_counting;
wire shift_ena;//與上一題目相比，shift_ena不需要輸出！
//狀態機第一部分
always@(posedge clk)begin
if(reset)
state <= S;
else
state <= next_state;
end
//狀態機的第二部分，狀態機和上一題目的一致！
always@(*)begin
case(state)
S:next_state=data?S1:S;
S1:next_state=data?S2:S;
S2:next_state=data?S2:S3;
S3:next_state=data?B0:S;
B0:next_state=B1;
B1:next_state=B2;
B2:next_state=B3;
B3:next_state=COUNT;
COUNT:next_state=done_counting?WAIT:COUNT;
WAIT:next_state=ack?S:WAIT;
endcase
end
//shift_ena和上一題目的一致，就是不需要輸出
//shift_ena拉高，表示已經檢測到1101
//後面就開始使用移位寄存器采取count數據，
assign shift_ena = (state == B0 || state == B1 || state == B2 || state == B3);
//使用移位寄存器采取count數據，
always@(posedge clk)begin
if(reset)
delay <= 0;
else if(shift_ena)
delay <= {delay[2:0], data};
end
//使用計數器，控制counting狀態
always@(posedge clk)begin
if(reset)
cnt_delay <= 0;
else
case(state)
COUNT:cnt_delay <= cnt_delay + 1;
default:cnt_delay <= 0;
endcase
end
//好好理解此處的題意
assign done_counting = (cnt_delay == (delay + 1) * 1000 - 1);
assign count = delay - cnt_delay / 1000;
assign counting = state == COUNT;
assign done = state == WAIT;
endmodule
