alex9ufo 聰明人求知心切

2013年12月30日星期一

Division

Division
- Division is another example of combining simple logic function to make a more complex circuit. Note that the method shown below ignores the divide-by-0 condition. (see also Multipliers and dividers)
- Algorithm 1: attempt subtraction
  - In calculating A / B, the divisor B is repeatedly subtracted from the digits of the dividend (A), after being multiplied either with ’1′ or with ’0′. This multiplication bit (’1′ or ’0′) is selected for each subtraction step in such a manner that the subtraction result is not negative. The division result is composed from all the successive multiplication bits while the remainder is the result of the last subtraction step.
  - This algorithm can be implemented by a series of subtractors. Each subtractor calculates the difference between two input numbers, but if the result is negative the operation is canceled and replaced with a subtraction of zero.
  - Each divider module:
    - contains a 1-bit subtractor with the usual inputs A, B and L_i and outputs D and L_o.
    - the output select (OS) signal selects between bit X and A-B. The signal is connected to the loan output (Lo) of the most significant 1-bit subtractor.
      - 0, means subtraction result was positive → D’ = D.
      - 1, means subtraction result was negative → D’ = X.
    - Inside each divider cell the OS signal selects between bitA and A-B.
    - The outputs can be expressed as a function of the inputs as in:
  - The complete division can therefore be implemented by a matrix of divider cells connected on rows and columns as shown in figure on the right.
  - Each row performs one multiplication-and-subtraction cycle where the multiplication bit is supplied by the NOT logic gate at the end of each row. (also see “Combinational arithmetic“)
  - The number of gates increases with the square width of the numbers being divided. This limits its use to designs where bit-width is relatively small, typically around 16 bits or below.

Multiplication

Multiplication
- Multiplication shows how simple logic functions can be combined to make a much more complex function.
- Method 1: partial products
  - The result of multiplying two n-bit numbers occupies up to 2×n bits.Multiplying the 4-bit numbers A and B can be written as A₃A₂A₁A0 × B₃B₂B₁B₀. The product can then be found by adding the partial products.
  - A basic building block can be made using:
    - Forming the partial product of two binary digits is simply an AND operation.
    - Adding the partial sums can be accomplished with 1-bit full adders.
  - These building blocks can then be used to build a 4-bit multiplier as shown in the figure below. (see also “Combinational multiplier“)
- Method 2: quarter squares
  - ¼·(A + B)² - ¼·(A – B)² = ¼·(A² + 2·A·B + B²) – ¼·(A² – 2·A·B + B²) =A·B
    - hard wire a look-up table of squares
    - calculate A + B, and look up C = (A + B)²
    - calculate A – B, and look up D = (A – B)²
    - calculate C – D, and divide by 4. The result is A × B^.
  - So three additions, two table look ups and divide by 4 (right shift by 2 bits).
  - The size of the look up tables scales nicely linear with the length of the operands.
    :

2013年12月29日星期日

FPGA系統設計實務 (5/6)

http://www.4shared.com/web/preview/doc/R_3O3-BU?

FPGA系統設計實務 (5/6)

2013年12月27日星期五

8bit x 8bits 乘法器轉BCD顯示於七段顯示器--適用於DE2-70

module _8x8bit_mul_BCD_7seg(SW,LEDR,HEX0 ,HEX1 ,HEX2,HEX3,,HEX4,HEX5,HEX6,HEX7);
input [15:0]SW;
output [15:0]LEDR;
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; //7-segment display

wire [7:0] a0,b0;

wire [3:0] S4,S3,S2,S1,S0;
wire [7:0] segout0; //HEX 0
wire [7:0] segout1; //HEX 1
wire [7:0] segout2; //HEX 2
wire [7:0] segout3; //HEX 3
wire [7:0] segout4; //HEX 4

wire [15:0] Product;

assign a0=SW[7:0];
assign b0=SW[15:8];

assign LEDR[15:0]=Product;

mult8S U0(Product,a0,b0);
BIN2BCD(Product,S4,S3,S2,S1,S0);

//Display BCD Sum to 7-segment Display

_7seg UUT0(.hex(S0),.seg(segout0));
_7seg UUT1(.hex(S1),.seg(segout1));
_7seg UUT2(.hex(S2),.seg(segout2));
_7seg UUT3(.hex(S3),.seg(segout3));
_7seg UUT4(.hex(S4),.seg(segout4));

assign HEX0=segout0[6:0];
assign HEX1=segout1[6:0];
assign HEX2=segout2[6:0];
assign HEX3=segout3[6:0];
assign HEX4=segout4[6:0];

assign HEX5=7'h7f; //Blank 7-segment
assign HEX6=7'h7f;
assign HEX7=7'h7f; //set 1 => off LED

endmodule

// ------------------------------------------------------------------------
//8-bit multiplier
//Filename : mult16S.v : P = A * B
//-------------------------------------------------------------------------
module mult8S(P,A,B);
output [15:0]P; // 32-bit product

input [7:0]A; //Multiplicand
input [7:0]B; //Multiplier

reg [15:0] p;
reg [15:0] temp;
reg [7:0] a;
reg [7:0] b;
integer i;

always @(A or B)
begin
a = A;
b = B;
if (a==0 || b==0) // q=0 when a or b equal 0
p = 15'b0;
else if (a==1) // q=b when a equal 1
p = {8'b0000_0000,b};
else if (b==1) // q=a when b equal 1
p = {8'b0000_0000,a};
else
begin
p = 15'b0;
for (i=0; i<8; i=i+1)
if (b[i] == 1)
begin
temp = a << i; // shift left N bits
p = p + temp;
end
end
end
assign P = p;

endmodule

module BIN2BCD(Binary,ten_thous,thousands,hundreds,tens,ones);

input [15:0]Binary;

output ten_thous;
output thousands;
output hundreds;
output tens;
output ones;

reg [3:0]ten_thous;
reg [3:0]thousands;
reg [3:0]hundreds;
reg [3:0]tens;
reg [3:0]ones;

integer i;

always@(Binary)
begin
ten_thous=4'd0;
thousands=4'd0;
hundreds=4'd0;
tens=4'd0;
ones=4'd0;

for (i=15; i>=0; i=i-1)
begin
//add 3 to column >=5 ;
if (ten_thous>=5)
ten_thous=ten_thous+3;

if (thousands>=5)
thousands=thousands+3;

if (hundreds>=5)
hundreds=hundreds+3;

if (tens>=5)
tens = tens + 3;

if (ones>=5)
ones = ones +3;

//shift left one bit
ten_thous=ten_thous<<1;
ten_thous[0]=thousands[3];

thousands=thousands<<1;
thousands[0]=hundreds[3];

hundreds=hundreds<<1;
hundreds[0]=tens[3];

tens=tens<<1;
tens[0]=ones[3];

ones=ones<<1;
ones[0]=Binary[i];

end

end

endmodule

//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//-----------------------------------------
module _7seg(hex , seg);
input [3:0] hex;
output [7:0] seg;
reg [7:0] seg;
// segment encoding
// 0
// ---
// 5 | | 1
// --- <- 6
// 4 | | 2
// ---
// 3
always @(hex)
begin
case (hex)
// Dot point is always disable
4'b0001 : seg = 8'b11111001; //1 = F9H
4'b0010 : seg = 8'b10100100; //2 = A4H
4'b0011 : seg = 8'b10110000; //3 = B0H
4'b0100 : seg = 8'b10011001; //4 = 99H
4'b0101 : seg = 8'b10010010; //5 = 92H
4'b0110 : seg = 8'b10000010; //6 = 82H
4'b0111 : seg = 8'b11111000; //7 = F8H
4'b1000 : seg = 8'b10000000; //8 = 80H
4'b1001 : seg = 8'b10010000; //9 = 90H
4'b1010 : seg = 8'b10001000; //A = 88H
4'b1011 : seg = 8'b10000011; //b = 83H
4'b1100 : seg = 8'b11000110; //C = C6H
4'b1101 : seg = 8'b10100001; //d = A1H
4'b1110 : seg = 8'b10000110; //E = 86H
4'b1111 : seg = 8'b10001110; //F = 8EH
default : seg = 8'b11000000; //0 = C0H
endcase
end

endmodule

8bit x 8bit 乘法器適用於DE2-70

8bit x 8bit 乘法器

module _8x8bit_mul(SW,LEDR);
input [15:0]SW;
output [15:0]LEDR;

wire [7:0]a0,b0;

assign a0=SW[7:0];
assign b0=SW[15:8];
mult8S U0(LEDR[15:0],a0,b0);

endmodule

// ------------------------------------------------------------------------
//8-bit multiplier
//Filename : mult16S.v : P = A * B
//-------------------------------------------------------------------------
module mult8S(P,A,B);
output [15:0]P; // 32-bit product

input [7:0]A; //Multiplicand
input [7:0]B; //Multiplier

reg [15:0] p;
reg [15:0] temp;
reg [7:0] a;
reg [7:0] b;
integer i;

always @(A or B)
begin
a = A;
b = B;
if (a==0 || b==0) // q=0 when a or b equal 0
p = 15'b0;
else if (a==1) // q=b when a equal 1
p = {8'b0000_0000,b};
else if (b==1) // q=a when b equal 1
p = {8'b0000_0000,a};
else
begin
p = 15'b0;
for (i=0; i<8; i=i+1)
if (b[i] == 1)
begin
temp = a << i; // shift left N bits
p = p + temp;
end
end
end
assign P = p;

endmodule

乘法器實驗方塊圖適用於DE2-70

訂閱：文章 (Atom)

2013年12月30日 星期一

2013年12月29日 星期日

2013年12月27日 星期五

2013年12月30日星期一

2013年12月29日星期日

2013年12月27日星期五