DE2-115 開發 以及閘AND Gate 為例(Verilog)

 DE2-115 開發 以及閘AND Gate 為例(Verilog)

//7408 AND Gate

module gate_7408_and( SW,LEDR );

input [17:0] SW;

output [17:0] LEDR;

and_gate(SW[17:0],LEDR[17:0]);

endmodule

//======================

//-- and_gate.v

//-- Component has an input (Din) and an output (Dout)

module and_gate( Din, Dout );

    input [17:0]Din;

    output [17:0]Dout;

    //-- Both the input and the output are "wires"

   wire [17:0]Din;

  wire [17:0]Dout;

      //-- Assign the nand of the input, to the output

    //gate-level modeling  

   and(Dout[0], Din[0], Din[1]);

   and (Dout[2], Din[2], Din[3]);

   // Data flow modeling

    assign Dout[4]= (Din[4] & Din[5]);

    assign Dout[6]= (Din[6] & Din[7]);

    assign Dout[8]= (Din[8] & Din[9]);

    assign Dout[10]= (Din[10] & Din[11]); 

   assign Dout[12]= (Din[12] & Din[13]); 

    assign Dout[14]= (Din[14] & Din[15]); 

    assign Dout[16]= (Din[16] & Din[17]); 

   //behavioral modeling

endmodule