以Verilog 設計第一個數位電路 程式---適用於DE2-70

Verilog 數位電路設計-範例寶典(基礎篇)（附光碟）

以Verilog 設計第一個數位電路 程式

(1) 將程式porting 到DE2-70 上實際測試 

//適用於DE2-70 

module module_demo(

  input CLOCK_50,     //    50 MHz clock

  input [3:0] KEY,      //    Pushbutton[3:0]

  input [17:0] SW,     //    Toggle Switch[17:0]

  output [6:0]    HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,  // Seven Segment Digits

  output [8:0] LEDG,   //    LED Green

  output [17:0] LEDR,   //    LED Red

  inout [35:0] GPIO_0,GPIO_1,    //    GPIO Connections

//    LCD Module 16X2

  output LCD_ON,     // LCD Power ON/OFF

  output LCD_BLON,     // LCD Back Light ON/OFF

  output LCD_RW,     // LCD Read/Write Select, 0 = Write, 1 = Read

  output LCD_EN,     // LCD Enable

  output LCD_RS,     // LCD Command/Data Select, 0 = Command, 1 = Data

  inout [7:0] LCD_DATA, // LCD Data bus 8 bits

  input  UART_RXD, //RS232 RXD

  output UART_TXD //RS232 TXD

);

//    All inout port turn to tri-state

assign    GPIO_0        =    36'hzzzzzzzzz;

assign    GPIO_1        =    36'hzzzzzzzzz;

wire  clk_25Mout ,clk_2sec;

assign HEX0=7'b111_1111;  //off 7-segment Display

assign HEX1=7'b111_1111;

assign HEX2=7'b111_1111;

assign HEX3=7'b111_1111;

assign HEX4=7'b111_1111;

assign HEX5=7'b111_1111;

assign HEX6=7'b111_1111;

assign HEX7=7'b111_1111;

// Send switches to red leds 

assign LEDR = SW;

//module_structure(a,b,c,d,en,sel,f);

module_structure(SW[0],SW[1],SW[2],SW[3],SW[17],SW[15],LEDG[0]);

endmodule

//++++++++++++++++++++++++++++++++++++++

module module_structure(a,b,c,d,en,sel,f);

input a,b,c,d,en,sel;

output f;

wire m1,m2,m3,m4;

assign m1=a | b ;  //OR

assign m2=c | d ;  

assign m3=en & m1 ; //AND

assign m4=en & m2 ;

assign f=(sel==0)? m3:m4 ; //sel==0  f=m3 , sel==1 f=m4

endmodule

//++++++++++++++++++++++++++++++++++++++

(2) 將程式porting 到ModelSim-Altera 軟體上測試 

//++++++++++++++++++++++++++++++++++++++

module module_demo(a,b,c,d,en,sel,f);

input a,b,c,d,en,sel;

output f;

wire m1,m2,m3,m4;

assign m1=a | b ;  //OR

assign m2=c | d ;  

assign m3=en & m1 ; //AND

assign m4=en & m2 ;

assign f=(sel==0)? m3:m4 ; //sel==0  f=m3 , sel==1 f=m4

endmodule

//Test bench

`timescale 1 ns/1 ns

module testbench;

reg a, b, c, d, en, sel;

wire f;

module_demo DUT (

.a(a),

.b(b),

.c(c),

.d(d),

.en(en),

.sel(sel),

.f(f) );

initial

begin

 a   = 1'b0; // Time = 0

 b   = 1'b1;

 c   = 1'b0;

 d   = 1'b1;

 en  = 1'b0;

 sel = 1'b0;

 #20; // Time = 20

 a  = 1'b1;

 #10; // Time = 30

 b  = 1'b0;

 c  = 1'b1;

 #10; // Time = 40

 a  = 1'b0;

 #10; // Time = 50

 en = 1'b1;

 #10; // Time = 60

 c  = 1'b0;

 #10; // Time = 70

 a  = 1'b1;

 d  = 1'b0;

 #20; // Time = 90

 c  = 1'b1;

 #20; // Time = 110

 a  = 1'b0;

 #10; // Time = 120

 a  = 1'b1;

 #10; // Time = 130

 c  = 1'b0;

 sel= 1'b1;

 #10; // Time = 140

 a  = 1'b0;

 #30; // Time = 170

 a  = 1'b1;

 #10; // Time = 180

 c  = 1'b1;

 #20; // Time = 200

 a  = 1'b0;

end

endmodule