16進制上數/下數 計數器(4bits) 含七段顯示器 適用於DE2-70 的程式 (2)---自動產生1Hz信號

//適用於DE2-70 的程式
module Cnt_load(
input [17:0]SW,
input [3:0] KEY,
input  CLOCK_50,

output [17:0] LEDR,
output [7:0] LEDG,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7
);

// assign HEX0=7'b111_1111;  //off 7-segment Display
assign HEX1=7'b111_1111;
assign HEX2=7'b111_1111;
assign HEX3=7'b111_1111;
assign HEX4=7'b111_1111;
assign HEX5=7'b111_1111;
assign HEX6=7'b111_1111;
assign HEX7=7'b111_1111;
assign LEDR[17:0]=SW[17:0];  //SW status =>LEDR
wire [3:0] cnt;
wire clk_1hz;

//clk_div_1hz(clk_in , Reset, clk_out);
clk_div_1hz u2(CLOCK_50, KEY[0], clk_1hz);
     
/*up_down_counter(
Load_in, //Load計數初值載入 
     Data_in, //計數初值 
     Clock, 
     Reset, 
     CounterON_in,    //計數器使能 
     UpDown_in,       //up/down 控制 
     CountResult_out  //計數結果 
     );  */

up_down_counter u0(SW[17],SW[3:0],clk_1hz,KEY[0],SW[16],SW[15],cnt);
hex_7seg u1(cnt,HEX0);
endmodule



module up_down_counter( 
     Load_in, //Load計數初值載入 
     Data_in, //計數初值 
     Clock, 
     Reset, 
     CounterON_in,  //計數器使能 
     UpDown_in,  //up/down 控制 
     CountResult_out //計數結果 
     ); 
     
    input Load_in; 
    input [3:0] Data_in; 
    input Clock; 
    input Reset; 
    input CounterON_in; 
    input UpDown_in; 
    output reg [3:0] CountResult_out;
    //reg [3:0] CountResult_out;; 
     
     always @(negedge Clock or negedge Reset) 
     begin 
      if(!Reset) 
         CountResult_out <= 'd0; 
      else if(Load_in) 
                CountResult_out <= Data_in; 
             else if(CounterON_in) 
                    begin 
                         if(UpDown_in) 
                            CountResult_out <= CountResult_out + 'd1; 
                         else 
                            CountResult_out <= CountResult_out - 'd1; 
                      end 
     end
endmodule 



module hex_7seg(hex_digit,seg);
input [3:0] hex_digit;
output [6:0] seg;
reg [6:0] seg;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off

always @ (hex_digit)
case (hex_digit)
  4'h0: seg = 7'b1000000;
  4'h1: seg = 7'b1111001;  // ---a----
  4'h2: seg = 7'b0100100;  // |   |
  4'h3: seg = 7'b0110000;  // f   b
  4'h4: seg = 7'b0011001;  // |   |
  4'h5: seg = 7'b0010010;  // ---g----
  4'h6: seg = 7'b0000010;  // |   |
  4'h7: seg = 7'b1111000;  // e   c
  4'h8: seg = 7'b0000000;  // |   |
  4'h9: seg = 7'b0011000;  // ---d----
  4'ha: seg = 7'b0001000;
  4'hb: seg = 7'b0000011;
  4'hc: seg = 7'b1000110;
  4'hd: seg = 7'b0100001;
  4'he: seg = 7'b0000110;
  4'hf: seg = 7'b0001110;
endcase
endmodule

module clk_div_1hz(clk_in , Reset, clk_out);
input clk_in ;
input Reset;
output reg  clk_out;

integer i;
always@(posedge clk_in or negedge Reset) begin
 if (!Reset) begin
   i=0;
   clk_out=0;
   end
 else begin
    i= i+1 ;
    if (i>=24_999_999) begin
        clk_out  = ~clk_out;
        i=0;
       end
    end    
end            

endmodule