FSM 紅綠燈--適用於DE2-70 ( EP2C35F672C6)

利用FSM 狀態機啟動紅綠燈 當SET=SW[0]=1時綠燈亮停1秒鐘,再轉為黃燈亮停2秒鐘,再轉為cj紅燈亮停5秒鐘,再轉為綠燈(初始狀態)

//FSM 紅綠燈--適用於DE2-70 ( EP2C35F672C6)

module FSM2(CLOCK_50, KEY[1:0],SW[1:0],LEDR[2:0]); //  LEDR[2:0]= green, yellow, red);

// module FSM2(clock, rst_n, set, green, yellow, red);
input CLOCK_50;     //clock;
input [1:0]KEY; //rst_n;
input [1:0]SW;   //set;
output [2:0] LEDR; //LEDR[2] green;  LEDR[1]=yellow; LEDR[0]=red;


reg [1:0] state, next_state;
reg green, yellow, red;

reg [4:0] count;
reg reset_count;

assign LEDR[0]=green;
assign LEDR[1]=yellow;
assign LEDR[2]=red;

wire rst_n ,clock_4Hz ,set ;
assign rst_n=KEY[0];
assign set=SW[0];

clock_div  u0(.CLOCK_50(CLOCK_50),.clock_4Hz(clock_4Hz) );
//控制器的狀態機(分開寫)

always@(posedge clock_4Hz, negedge rst_n)
begin
if(!rst_n) state <= 2'd0;
else state <= next_state;
 end

////////////////////////////////////
always@(state or set or count)
begin
case(state)
 2'd0:
if(set == 1'b1)
next_state=2'd1;
else
next_state=2'd0;
 2'd1:
if( count==5'd4 )
next_state=2'd2;
else
next_state=2'd1;
2'd2:
if( count==5'd8 )
next_state=2'd0;
else
next_state=2'd2;
  default:
next_state = 2'd0;
endcase
 end


//在每個狀態下，輸出的號誌燈訊號
always@(state)
begin
        case(state)
        2'd0: begin
                   green =1'b1;
                   yellow =1'b0;
                   red =1'b0;
                  end

        2'd1: begin
                   green =1'b0;
                   yellow =1'b1;
                   red =1'b0;
                  end

        2'd2: begin
                   green =1'b0;
                   yellow =1'b0;
                   red =1'b1;
                  end

    default:begin
                   green =1'b0;
                   yellow =1'b0;
                   red =1'b0;
                  end
        endcase
end
//重新啟動計數器的裝置
always@(posedge clock_4Hz)
  begin
    if(state!=next_state)
      reset_count <= 1'b1;
    else
      reset_count <= 1'b0;
  end

//計數器
always@(posedge clock_4Hz or posedge reset_count)

  if(reset_count == 1'b1)
    count <= 5'd0;
  else
    count <= count + 5'd1;

endmodule








module clock_div( CLOCK_50, clock_4Hz );
input CLOCK_50;
output clock_4Hz;
reg [25:0] count_4Hz;
reg clock_4Hz;
//====================================
// 50MHz => 4 Hz
//====================================
always@(posedge CLOCK_50)
begin
if( count_4Hz < 26'd12_500_000 )
  count_4Hz <= count_4Hz + 26'd1;
else
  count_4Hz <= 26'd00_000_001;
 end
always@(posedge CLOCK_50)
begin
  if( count_4Hz <= 26'd6_250_000 )
    clock_4Hz <= 1'd1;
else
    clock_4Hz <= 1'd0;
end
endmodule