16bits Binary to BCD Converter---適用於DE2-70 的程式

16bits Binary to BCD Converter ( Shift and Add-3 Algorithm) 二進制轉BCD ---適用於DE2-70 的程式 

SW[15:0]=Binary Data

HEX4:HEX0=BCD Data

module Bin2BCD(  //適用於DE2-70 的程式

 input [17:0]SW,

 input [3:0] KEY,

 input  CLOCK_50,

 output [17:0] LEDR,

 output [8:0] LEDG,

 output [6:0] HEX0,

 output [6:0] HEX1,

 output [6:0] HEX2,

 output [6:0] HEX3,

 output [6:0] HEX4,

 output [6:0] HEX5,

 output [6:0] HEX6,

 output [6:0] HEX7

 );

//assign HEX0=7'b111_1111;  //off 7-segment Display

//assign HEX1=7'b111_1111;

//assign HEX2=7'b111_1111;

//assign HEX3=7'b111_1111;

//assign HEX4=7'b111_1111;

assign HEX5=7'b111_1111;

assign HEX6=7'b111_1111;

assign HEX7=7'b111_1111;

wire [3:0]ONES,TENS,HUNDREDS,THOUSAND,TEN_THOU;

assign LEDR[15:0]=SW[15:0];

binary_to_BCD u0(SW[15:0],ONES,TENS,HUNDREDS,THOUSAND,TEN_THOU);

hex_7seg u1(ONES,HEX0);

hex_7seg u2(TENS,HEX1);

hex_7seg u3(HUNDREDS,HEX2);

hex_7seg u4(THOUSAND,HEX3);

hex_7seg u5(TEN_THOU,HEX4);

endmodule

module binary_to_BCD(A,ONES,TENS,HUNDREDS,THOUSAND,TEN_THOU);

input [15:0] A;

output reg [3:0] ONES, TENS;

output reg [3:0] HUNDREDS,THOUSAND,TEN_THOU;

integer i;

always@(A)

begin 

        TEN_THOU=4'd0;

    THOUSAND=4'd0;

HUNDREDS=4'd0;

TENS=4'd0;

ONES=4'd0;

    

    for(i=15;i>=0;i=i-1)

    begin  

      //Add 3 to columns >=5

      if (TEN_THOU>=5)

          TEN_THOU=TEN_THOU+3;

      if (THOUSAND >=5)

        THOUSAND=THOUSAND+3;

      if (HUNDREDS >=5)

         HUNDREDS=HUNDREDS+3;

      if (TENS >=5)

        TENS=TENS+3;

      if (ONES >=5)

         ONES=ONES+3;

            

      //Shift left one

      TEN_THOU=TEN_THOU<<1;

      TEN_THOU[0]=THOUSAND[3];

      

      THOUSAND=THOUSAND<<1;

      THOUSAND[0]=HUNDREDS[3];

      

      HUNDREDS=HUNDREDS<<1;

      HUNDREDS[0]=TENS[3];

      

      TENS=TENS<<1;

      TENS[0]=ONES[3];

      

      ONES=ONES<<1;

      ONES[0]=A[i];

   

end

end

endmodule

module hex_7seg(hex_digit,seg);

input [3:0] hex_digit;

output [6:0] seg;

reg [6:0] seg;

// seg = {g,f,e,d,c,b,a};

// 0 is on and 1 is off

always @ (hex_digit)

case (hex_digit)

  4'h0: seg = 7'b1000000;

  4'h1: seg = 7'b1111001;  // ---a----

  4'h2: seg = 7'b0100100;  // |   |

  4'h3: seg = 7'b0110000;  // f   b

  4'h4: seg = 7'b0011001;  // |   |

  4'h5: seg = 7'b0010010;  // ---g----

  4'h6: seg = 7'b0000010;  // |   |

  4'h7: seg = 7'b1111000;  // e   c

  4'h8: seg = 7'b0000000;  // |   |

  4'h9: seg = 7'b0011000;  // ---d----

  4'ha: seg = 7'b0001000;

  4'hb: seg = 7'b0000011;

  4'hc: seg = 7'b1000110;

  4'hd: seg = 7'b0100001;

  4'he: seg = 7'b0000110;

  4'hf: seg = 7'b0001110;

endcase

endmodule