實現一個FSM用於識別2中指定的輸入序列：4個1或4個0。輸入信號為w，輸出為z。當連續4個時鐘w=1或0時，z=1；否則，z=0.序列允許重合，比如連續5個時鐘w=1，在第4,5個時鐘z=1。圖1描述了w和z的關係。
/* ( module one_hot (reset,clock,w,Y);
input reset;
input clock;
input w;
tri0 reset;
tri0 w;
output Y; */
reg Y;
reg [8:0] fstate;
reg [8:0] reg_fstate;
wire reset , w ,clock ;
assign reset = KEY[0];
assign clock = KEY[1];
assign w = SW[0];
assign LEDG[0]=Y;
parameter A=8'd0,B=8'd1,C=8'd2,D=8'd3,E=8'd4,F=8'd5,G=8'd6,H=8'd7,I=8'd8;
always @(negedge clock )
begin
if(!clock==1)
fstate <= reg_fstate;
end
always @(fstate or reset or w)
begin
if (!reset) begin
reg_fstate <= A;
Y <= 1'b0;
end
else begin
Y <= 1'b0;
case (fstate)
A: begin
if (~(w))
reg_fstate <= B;
else if (w)
reg_fstate <= F;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= A;
if (~(w))
Y <= 1'b0;
else if (w)
Y <= 1'b0;
// Inserting 'else' block to prevent latch inference
else
Y <= 1'b0;
end
B: begin
if (~(w))
reg_fstate <= C;
else if (w)
reg_fstate <= F;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= B;
if (~(w))
Y <= 1'b0;
else if (w)
Y <= 1'b0;
// Inserting 'else' block to prevent latch inference
else
Y <= 1'b0;
end
C: begin
if (~(w))
reg_fstate <= D;
else if (w)
reg_fstate <= F;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= C;
if (~(w))
Y <= 1'b0;
else if (w)
Y <= 1'b0;
// Inserting 'else' block to prevent latch inference
else
Y <= 1'b0;
end
D: begin
if (~(w))
reg_fstate <= E;
else if (w)
reg_fstate <= F;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= D;
if (~(w))
Y <= 1'b0;
else if (w)
Y <= 1'b0;
// Inserting 'else' block to prevent latch inference
else
Y <= 1'b0;
end
E: begin
if (~(w))
reg_fstate <= E;
else if (w)
reg_fstate <= F;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= E;
if (w)
Y <= 1'b1;
else if (~(w))
Y <= 1'b1;
// Inserting 'else' block to prevent latch inference
else
Y <= 1'b0;
end
F: begin
if (~(w))
reg_fstate <= B;
else if (w)
reg_fstate <= G;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= F;
if (w)
Y <= 1'b0;
else if (~(w))
Y <= 1'b0;
// Inserting 'else' block to prevent latch inference
else
Y <= 1'b0;
end
G: begin
if (w)
reg_fstate <= H;
else if (~(w))
reg_fstate <= B;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= G;
if (w)
Y <= 1'b0;
else if (~(w))
Y <= 1'b0;
// Inserting 'else' block to prevent latch inference
else
Y <= 1'b0;
end
H: begin
if (w)
reg_fstate <= I;
else if (~(w))
reg_fstate <= B;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= H;
if (w)
Y <= 1'b0;
else if (~(w))
Y <= 1'b0;
// Inserting 'else' block to prevent latch inference
else
Y <= 1'b0;
end
I: begin
if (w)
reg_fstate <= I;
else if (~(w))
reg_fstate <= B;
// Inserting 'else' block to prevent latch inference
else
reg_fstate <= I;
if (w)
Y <= 1'b1;
else if (~(w))
Y <= 1'b1;
// Inserting 'else' block to prevent latch inference
else
Y <= 1'b0;
end
default: begin
Y <= 1'bx;
$display ("Reach undefined state");
end
endcase
end
end
endmodule
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