Verilog HDL: Expressions, Operators and Operands

源自 http://asic-soc.blogspot.tw/2011/11/verilog-hdl-expressions-operators-and.html

Verilog HDL: Expressions, Operators and Operands

Dataflow modeling in Verilog describes the design in terms of expressions, instead of primitive gates. ‘expressions,, ‘operators’ and ‘operands’ form the basis of Verilog dataflow modeling.

Arithmetic:

                            *       ---> Multiplication
                            /        ---> Division
                           +        ---> Addition
                           -         ---> Subtraction
                           %       ---> Modulo
                          **        ---> Power or exponent

Logical:

                           !         ---> logical negation (one operand)
                       &&       ---> logical AND
                           ||         ---> logical OR

Relational:

                          >        ---> greater than

                          <        ---> lesser than

                          >=      ---> gretaer than or equal to

                          <=      ---> less than or equal to

Equality:

                          ==      ---> equality
                          !=       ---> inequality
                       ===       ---> case equality
                        !==       ---> case inequality

Bitwise:

                          ~        ---> bitwise negation (one operand)
                         &        ---> bitwise AND
                          |          ---> bitwise OR
                         ^         ---> bitwise XOR
             ^~ or ~^         ---> bitwise XNOR

Reduction:

                         &          ---> reduction and (one operand)
                       ~&          ---> reduction NAND
                          |            ---> reduction OR
                        ~|            ---> reduction NOR
                         ^           ---> reduction XOR
              ^~ or ~^          ---> reduction XNOR

Shift:

                       >>           ---> right shift
                      <<            ---> left shift
                    >>>            ---> arithmetic right shift
                    <<<            ---> arithmetic left shift

Concatenation:

                          { }        ---> any number operand

Eg:

         A= 1’b1, B=2’b00, C =2’b10, D=3’b110
         Y={B,C}                                                 //result y is 4’b0010
         Y={A,B,C,D,3’b001}                            //y=11’b10010110001
         Y={A,B[0],C[1]}                                   //Y=3’b101


Replication:

                       {{ }}        ---> any number operand

Eg :- 
           reg A;
           reg [1:0] B,C;
           reg [2:0] D;
          A=11b1; B=2’b00; C=2’b10; D=3’b110;

          Y={4{A}}                                              //result y is 4’b1111
          Y={4{A} , 2{B}}                                  //y=8’b11110000
          Y={4{A},2{B},C}                                //y=8’b1111000010


Conditional:

                          ?: (three operands)