4bit 4channel 解多工暫存器 ---適用於DE2-70

 module DeMux_4ch_4bit(CLOCK_50,KEY,SW,LEDR);

 input CLOCK_50; //50MHz時鐘
 input [0:0]KEY; //重置 reset
 input  [17:0]SW ;
 output [17:0] LEDR;

EX_demuxed_reg (KEY[0],CLOCK_50,SW[17:16],SW[3:0],LEDR[15:12],LEDR[11:8],LEDR[7:4],LEDR[3:0]);

ednmodule





module EX_demuxed_reg (reset, clk, sel, f, a, b, c, d);
input reset, clk;
input [1:0] sel;
/*  配合DE2-70 改成4bits
input [7:0] f;
output [7:0] a, b, c, d;
wire [7:0] a, b, c, d;
reg [7:0] a_reg, b_reg, c_reg, d_reg;

*/
input [3:0] f;
output [3:0] a, b, c, d;
wire [3:0] a, b, c, d;
reg [3:0] a_reg, b_reg, c_reg, d_reg;


assign a = a_reg;
assign b = b_reg;
assign c = c_reg;
assign d = d_reg;

always@(posedge clk or negedge reset)
begin
  if(!reset) begin
     /*配合DE2-70 改成4bits
    a_reg <=  8'h00;
    b_reg <=  8'h00;
    c_reg <=  8'h00;
    d_reg <=  8'h00;
    */
    a_reg <=  4'h00;
    b_reg <=  4'h00;
    c_reg <=  4'h00;
    d_reg <=  4'h00;
  end
  else
    case (sel)
      2'b00 :   a_reg <=  f;
      2'b01 :   b_reg <=  f;
      2'b10 :   c_reg <=  f;
      2'b11 :   d_reg <=  f;
      default : a_reg <=  f;
    endcase
end

endmodule