時鐘分頻
把DE2上的50MHz的時鐘分成以下7種：
在top module 將50MHZ 分頻得到的7個時鐘組成的數組叫做myclock。
2. 十進制計數器 用1Hz的時鐘驅動2個十進制的計數器,並將其輸出顯示在HEX7-6上2個進位信號分別接 到LEDG7和LEDG6. 00--99
/* File name: ex1_2.v
* Function: This lab illustrates the use of divide-by-N counters, decimal counters,
*/
module ex1_2 (
// clock input (50 MHz)
input CLOCK_50,
// push buttons
input [3:0] KEY,
// dpdt switches
input [17:0] SW,
// 7-seg display
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,
// leds
output [8:0] LEDG, //LED Green [8:0]
output [17:0] LEDR, // LED Red[17:0]
// GPIO Connections
inout [35:0] GPIO_0, GPIO_1
);
// set all inout port to tri-state
assign GPIO_0 = 36'hzzzzzzzzz;
assign GPIO_1 = 36'hzzzzzzzzz;
wire [6:0] myclock;
wire RST;
assign RST = KEY[0];
// setup clock divider
clock_divider cdiv (CLOCK_50, RST, myclock);
assign GPIO_0[6:0] = myclock;
// connect clock divider to green leds
assign LEDG[4:0] = myclock[4:0];
// connect dip switches to red leds
assign LEDR[17:0] = SW[17:0];
// set up counters
wire [3:0] digit7, digit6;
wire ovr0, ovr1;
decimal_counter count0 (digit6, ovr0, myclock[0], RST);
decimal_counter count1 (digit7, ovr1, ovr0, RST);
// map to 7-segment displays
hex_7seg dsp0 (digit6, HEX6);
hex_7seg dsp1 (digit7, HEX7);
assign LEDG[7] = ovr1;
assign LEDG[6] = ovr0;
// turn unused LEDs off
assign LEDG[8] = 1'b0;
assign LEDG[5] = 1'b0;
// define a simple hex counter
reg [3:0] A;
always @(posedge myclock[0] or negedge RST)
begin
if (~RST)
A <= 4'b0000;
else
A <= A+1'b1;
end
hex_7seg dsp2 (A, HEX0);
// blanks remaining digits
assign HEX1 = 7'b111_1111;
assign HEX2 = 7'b111_1111;
assign HEX3 = 7'b111_1111;
assign HEX4 = 7'b111_1111;
assign HEX5 = 7'b111_1111;
endmodule
/* File name: decimal_counter.v
*/
module decimal_counter (A, OVERFLOW, CLK, RST);
input CLK, RST;
output OVERFLOW;
output [3:0] A;
reg OVERFLOW;
reg [3:0] A;
always @(posedge CLK or negedge RST)
if (~RST) begin
OVERFLOW <= 1'b0;
A <= 4'b0000;
end
else if (A < 9) begin
A <= A + 1'b1;
OVERFLOW <= 1'b0;
end
else begin
A <= 4'b0000;
OVERFLOW <= 1'b1;
end
endmodule
/* File name: clock_divider.v
*/
module clock_divider (CLK, RST, clock);
input CLK, RST;
output [6:0] clock;
wire clk_1MHz, clk_100KHz, clk_10KHz, clk_1KHz, clk_100Hz, clk_10Hz, clk_1Hz;
assign clock = {clk_1MHz, clk_100KHz, clk_10KHz, clk_1KHz, clk_100Hz, clk_10Hz, clk_1Hz};
divide_by_50 d6 (clk_1MHz, CLK, RST);
divide_by_10 d5 (clk_100KHz, clk_1MHz, RST);
divide_by_10 d4 (clk_10KHz, clk_100KHz, RST);
divide_by_10 d3 (clk_1KHz, clk_10KHz, RST);
divide_by_10 d2 (clk_100Hz, clk_1KHz, RST);
divide_by_10 d1 (clk_10Hz, clk_100Hz, RST);
divide_by_10 d0 (clk_1Hz, clk_10Hz, RST);
endmodule
/* File name: divide_by_10.v
*/
module divide_by_10 (Q, CLK, RST,);
input CLK, RST;
output Q;
reg Q;
reg [2:0] count;
always @(posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 3'b000;
end
else if (count < 4)
begin
count <= count + 1'b1;
end
else
begin
count <= 3'b000;
Q <= ~Q;
end
end
endmodule
/* File name: divide_by_50.v
50 = 25 * 2 divide_by_2 & divide_by_25
*/
module divide_by_50 (Q, CLK, RST);
input CLK, RST;
output Q;
reg Q;
reg [4:0] count;
always @(posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 5'b00000;
end
else if (count < 24)
begin
count <= count + 1'b1;
end
else
begin
count <= 5'b00000;
Q <= ~Q;
end
end
endmodule
/* File name : hex_7seg.v
*/
module hex_7seg (hex_digit, seg);
input [3:0] hex_digit;
output [6:0] seg;
reg [6:0] seg;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off
always @(hex_digit)
case(hex_digit)
4'h0: seg = ~7'h3F;
4'h1: seg = ~7'h06; // ---a----
4'h2: seg = ~7'h5B; // | |
4'h3: seg = ~7'h4F; // f b
4'h4: seg = ~7'h66; // | |
4'h5: seg = ~7'h6D; // ---g----
4'h6: seg = ~7'h7D; // | |
4'h7: seg = ~7'h07; // e c
4'h8: seg = ~7'h7F; // | |
4'h9: seg = ~7'h67; // ---d----
4'ha: seg = ~7'h77;
4'hb: seg = ~7'h7C;
4'hc: seg = ~7'h39;
4'hd: seg = ~7'h5E;
4'he: seg = ~7'h79;
4'hf: seg = ~7'h71;
endcase
endmodule
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