alex9ufo 聰明人求知心切

2021年3月27日星期六

DE2-115 開發以 monostable 為例

module monostable (SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,HEX4 ,HEX5 ,HEX6,HEX7, GPIO );
input [17:0] SW; // toggle switches
input [7:0] KEY; // Push bottom
input CLOCK_50; //Clock 27MHz , 50Mhz
output [17:0] LEDR; // red LEDS
output [8:0] LEDG; // green LEDs
output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display
output [6:0] HEX4,HEX5,HEX6,HEX7; //7-segment display
inout [35:0] GPIO;
assign HEX0=7'b111_1111;
assign HEX1=7'b111_1111;
assign HEX2=7'b111_1111;
assign HEX3=7'b111_1111;
assign HEX4=7'b111_1111;
assign HEX5=7'b111_1111;
assign HEX6=7'b111_1111;
assign HEX7=7'b111_1111;
wire oClk_1MHz,oClk100K,oClk10K,oClk1K,oClk100,oClk10,oClk1 ;
MHz50_1MHz u1 (CLOCK_50,KEY[0],oClk_1MHz);
clk_1Hz u2 (oClk_1MHz,KEY[0],oClk100K,oClk10K,oClk1K,oClk100,oClk10,oClk1,oClk01);

//module delayed_monostable(input clk,
// input reset,input trigger,output pulse
delayed_monostable (oClk10,SW[0],SW[1],LEDR[0]);
endmodule

module delayed_monostable(
input clk,
input reset,
input trigger,
output pulse
);
parameter DELAY_WIDTH = 50;
parameter SIGNAL_WIDTH = 50;
wire dly;
monostable_one_shot #(.PULSE_WIDTH(DELAY_WIDTH)) delay(
.clk(clk),
.reset(reset),
.trigger(trigger),
.pulse(dly)
);
wire trig = ~dly;
monostable_one_shot #(.PULSE_WIDTH(SIGNAL_WIDTH)) signal(
.clk(clk),
.reset(reset),
.trigger(trig),
.pulse(pulse)
);
endmodule
module monostable_one_shot(
input clk,
input reset,
input trigger,
output reg pulse = 0
);
parameter PULSE_WIDTH = 50;
reg [5:0] count = 0;
wire count_rst = reset | (count == PULSE_WIDTH);
always @ (posedge trigger, posedge count_rst) begin
if (count_rst) begin
pulse <= 1'b0;
end else begin
pulse <= 1'b1;
end
end
always @ (posedge clk, posedge count_rst) begin
if(count_rst) begin
count <= 0;
end else begin
if(pulse) begin
count <= count + 1'b1;
end
end
end
endmodule
//Clock 50MHz --> 1MHz
module MHz50_1MHz(Clk_in , Clr , Clk_out); //除50
input Clk_in , Clr; // 一位元輸入
output reg Clk_out;
reg [4:0] cnt=5'b0_0000;
// counter size calculation according to input and output frequencies
parameter sys_clk = 50000000; // 50 MHz system clock
parameter clkout = 1000000; // 1 MHz clock output
parameter max = sys_clk / (2*clkout); // max-counter size
always@(posedge Clk_in or negedge Clr ) begin
if (~Clr)
begin
cnt <= 0;
end
else if (cnt == max-1 )
begin
cnt <= 0;
Clk_out <= ~Clk_out;
end
else
begin
cnt <= cnt + 1'd1;
end
end
endmodule

// Ch10 clk_1Hz.v
// 由 10M Hz 除頻至 1 Hz
module clk_1Hz (Clk1M,Clr,Clk100K,Clk10K,Clk1K,Clk100,Clk10,Clk1,Clk01);
input Clk1M,Clr; // 一位元輸入
output Clk100K,Clk10K,Clk1K,Clk100,Clk10,Clk1,Clk01; // 一位元輸出
div10 D2 (Clk1M , Clr, Clk100K);
div10 D3 (Clk100K, Clr, Clk10K );
div10 D4 (Clk10K , Clr, Clk1K );
div10 D5 (Clk1K , Clr, Clk100 );
div10 D6 (Clk100 , Clr, Clk10 );
div10 D7 (Clk10 , Clr, Clk1 );
div10 D8 (Clk1 , Clr, Clk01 );
endmodule

// Ch10 div10.v
// 除頻 /10
module div10 (Clk_i,Clr,Clk_o);
input Clk_i,Clr; // 一位元輸入
output Clk_o; // 一位元輸出
reg Clk_o; // 宣告為暫存器資料
reg [3:0] Q; // 宣告為暫存器資料
// MOD-10 (BCD) 除頻
always@ (posedge Clk_i or negedge Clr)
if (~Clr )
Q = 0;
else if (Q == 9)
Q = 0;
else
Q = Q + 1;
// 形成對稱方波
always@ (Q)
if (Q <= 4)
Clk_o = 0;
else
Clk_o = 1;
endmodule

DE2-115 開發以 Creating pulses of different width 為例

SW[1:0]=select different width

LEDR[13:0]=show select different width

LEDR[14] ,LEDR[15],LEDR[16],LEDR[17]

module x74121_oneshot (SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,HEX4 ,HEX5 ,HEX6,HEX7, GPIO );

input [17:0] SW; // toggle switches

input [7:0] KEY; // Push bottom

input CLOCK_50; //Clock 27MHz , 50Mhz

output [17:0] LEDR; // red LEDS

output [8:0] LEDG; // green LEDs

output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display

output [6:0] HEX4,HEX5,HEX6,HEX7; //7-segment display

inout [35:0] GPIO;

assign HEX0=7'b111_1111;

assign HEX1=7'b111_1111;

assign HEX2=7'b111_1111;

assign HEX3=7'b111_1111;

assign HEX4=7'b111_1111;

assign HEX5=7'b111_1111;

assign HEX6=7'b111_1111;

assign HEX7=7'b111_1111;

wire oClk_1MHz,oClk100K,oClk10K,oClk1K,oClk100,oClk10,oClk1 ;

MHz50_1MHz u1 (CLOCK_50,KEY[0],oClk_1MHz);

clk_1Hz u2 (oClk_1MHz,KEY[0],oClk100K,oClk10K,oClk1K,oClk100,oClk10,oClk1,oClk01);

assign LEDR[17]= oClk01;

//oneshot(BUFFER_IN,BUFFER_OUT,CLK);

one_pluse(SW[1:0],oClk_1MHz,KEY[0],LEDR[14],LEDR[13:0],LEDR[15],LEDR[16]);

endmodule

module one_pluse(input wire [1:0] sel , //selection lines s1 s0

input clk,

input rst_n,

output reg flag, //for checking conditions

output reg [13:0] Q, // output of 14 bit counter

output reg pulse, //output pulse

output reg count); //also for checking conditions

wire flag_d , count_d;

assign flag_d = ( (sel == 2'b00 | sel == 2'b01 | sel == 2'b10 | sel == 2'b11) && count == 1'b0)? 1'b1 : flag;

assign count_d = ( (sel == 2'b00 | sel == 2'b01 | sel == 2'b10 | sel == 2'b11) && count == 1'b0)? 1'b1 : count;

always @(posedge clk , negedge rst_n)

begin

if(!rst_n)

begin

Q <= 14'h0;

count <= 1'b0;

pulse <= 1'b0;

flag <= 1'b0;

end

else

begin

flag <= flag_d;

count <= count_d;

if(flag)

begin

case(sel)

2'b00: Q <= 14'd11;//count from 11 to 1

2'b01: Q <= 14'd101;//count from 101 to 1

2'b10: Q <= 14'd1001;//count from 1001 to 1

2'b11: Q <= 14'd10001;//count from 10001 to 1

default: Q <= 14'd0;

endcase

flag <= 1'b0;

end

else

begin

if(Q != 14'h1 && Q != 14'h0)

begin

Q <= Q - 14'h1;

pulse <= 1'b1;

end

else

begin

pulse <= 1'b0;

count <= 1'b0;

end

endmodule

//Clock 50MHz --> 1MHz

module MHz50_1MHz(Clk_in , Clr , Clk_out); //除50

input Clk_in , Clr; // 一位元輸入

output reg Clk_out;

reg [4:0] cnt=5'b0_0000;

// counter size calculation according to input and output frequencies

parameter sys_clk = 50000000; // 50 MHz system clock

parameter clkout = 1000000; // 1 MHz clock output

parameter max = sys_clk / (2*clkout); // max-counter size

always@(posedge Clk_in or negedge Clr ) begin

if (~Clr)

begin

cnt <= 0;

end

else if (cnt == max-1 )

begin

cnt <= 0;

Clk_out <= ~Clk_out;

end

else

begin

cnt <= cnt + 1'd1;

end

endmodule

// Ch10 clk_1Hz.v

// 由 10M Hz 除頻至 1 Hz

module clk_1Hz (Clk1M,Clr,Clk100K,Clk10K,Clk1K,Clk100,Clk10,Clk1,Clk01);

input Clk1M,Clr; // 一位元輸入

output Clk100K,Clk10K,Clk1K,Clk100,Clk10,Clk1,Clk01; // 一位元輸出

div10 D2 (Clk1M , Clr, Clk100K);

div10 D3 (Clk100K, Clr, Clk10K );

div10 D4 (Clk10K , Clr, Clk1K );

div10 D5 (Clk1K , Clr, Clk100 );

div10 D6 (Clk100 , Clr, Clk10 );

div10 D7 (Clk10 , Clr, Clk1 );

div10 D8 (Clk1 , Clr, Clk01 );

endmodule

// Ch10 div10.v

// 除頻 /10

module div10 (Clk_i,Clr,Clk_o);

input Clk_i,Clr; // 一位元輸入

output Clk_o; // 一位元輸出

reg Clk_o; // 宣告為暫存器資料

reg [3:0] Q; // 宣告為暫存器資料

// MOD-10 (BCD) 除頻

always@ (posedge Clk_i or negedge Clr)

if (~Clr )

Q = 0;

else if (Q == 9)

Q = 0;

else

Q = Q + 1;

// 形成對稱方波

always@ (Q)

if (Q <= 4)

Clk_o = 0;

else

Clk_o = 1;

endmodule

2021年3月26日星期五

DE2-115 開發以 7493 4bit Binary counter 為例(Verilog behavioral modeling )

module Counter_4bit (SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,HEX4 ,HEX5 ,HEX6,HEX7, GPIO );

input [17:0] SW; // toggle switches

input [7:0] KEY; // Push bottom

input CLOCK_50; //Clock 27MHz , 50Mhz

output [17:0] LEDR; // red LEDS

output [8:0] LEDG; // green LEDs

output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display

output [6:0] HEX4,HEX5,HEX6,HEX7; //7-segment display

inout [35:0] GPIO;

assign HEX0=7'b111_1111;

assign HEX1=7'b111_1111;

assign HEX2=7'b111_1111;

assign HEX3=7'b111_1111;

assign HEX4=7'b111_1111;

assign HEX5=7'b111_1111;

assign HEX6=7'b111_1111;

assign HEX7=7'b111_1111;

wire oClk_1MHz,oClk100K,oClk10K,oClk1K,oClk100,oClk10,oClk1 ;

MHz50_1MHz u1 (CLOCK_50,KEY[0],oClk_1MHz);

clk_1Hz u2 (oClk_1MHz,KEY[0],oClk100K,oClk10K,oClk1K,oClk100,oClk10,oClk1,oClk01);

//將1Hz Clock /10 =oClk01 送給 4 bit counter 的Clock

x7493(oClk01,SW[0],SW[1],LEDR[3:0]);

endmodule

module x7493(input_clock,counter_en1, counter_en2,counter_register);

input input_clock; // declares the input

input counter_en1, counter_en2 ; //counter enable

output reg [3:0] counter_register;

// declares the output to be a 4-bit register

initial // initial block to set the counter to zero

begin

// The next line sets counter register to zero

counter_register = 4'b0000;

end

always@ (posedge input_clock or negedge counter_en1 or negedge counter_en2 )

begin

// the following line increments the register by

// 1 at each clock trigger

if (~counter_en1)

begin

counter_register <= 0;

end

else if (~counter_en2 )

begin

counter_register <= 0;

end

else

counter_register <= counter_register + 4'b0001;

end

endmodule

//Clock 50MHz --> 1MHz

module MHz50_1MHz(Clk_in , Clr , Clk_out); //除50

input Clk_in , Clr; // 一位元輸入

output reg Clk_out;

reg [4:0] cnt=5'b0_0000;

// counter size calculation according to input and output frequencies

parameter sys_clk = 50000000; // 50 MHz system clock

parameter clkout = 1000000; // 1 MHz clock output

parameter max = sys_clk / (2*clkout); // max-counter size

always@(posedge Clk_in or negedge Clr ) begin

if (~Clr)

begin

cnt <= 0;

end

else if (cnt == max-1 )

begin

cnt <= 0;

Clk_out <= ~Clk_out;

end

else

begin

cnt <= cnt + 1'd1;

end

endmodule

// Ch10 clk_1Hz.v

// 由 10M Hz 除頻至 1 Hz

module clk_1Hz (Clk1M,Clr,Clk100K,Clk10K,Clk1K,Clk100,Clk10,Clk1,Clk01);

input Clk1M,Clr; // 一位元輸入

output Clk100K,Clk10K,Clk1K,Clk100,Clk10,Clk1,Clk01; // 一位元輸出

div10 D2 (Clk1M , Clr, Clk100K);

div10 D3 (Clk100K, Clr, Clk10K );

div10 D4 (Clk10K , Clr, Clk1K );

div10 D5 (Clk1K , Clr, Clk100 );

div10 D6 (Clk100 , Clr, Clk10 );

div10 D7 (Clk10 , Clr, Clk1 );

div10 D8 (Clk1 , Clr, Clk01 );

endmodule

// Ch10 div10.v

// 除頻 /10

module div10 (Clk_i,Clr,Clk_o);

input Clk_i,Clr; // 一位元輸入

output Clk_o; // 一位元輸出

reg Clk_o; // 宣告為暫存器資料

reg [3:0] Q; // 宣告為暫存器資料

// MOD-10 (BCD) 除頻

always@ (posedge Clk_i or negedge Clr)

if (~Clr )

Q = 0;

else if (Q == 9)

Q = 0;

else

Q = Q + 1;

// 形成對稱方波

always@ (Q)

if (Q <= 4)

Clk_o = 0;

else

Clk_o = 1;

endmodule

DE2-115 開發以 74138解碼器為例(Verilog data flow modeling )

參考來源https://www.programmersought.com/article/34964783614/

// 74138 decoder

module Decoder_3x8_74138(SW,LEDR );

input [17:0] SW;

output [17:0] LEDR;

x74138(SW[15:13],SW[2:0],LEDR[7:0]);

endmodule

module x74138(En, I, O);

input wire[2:0] En; //active enable=[100]

input wire[2:0] I;

output wire[7:0] O;

assign O = (En==3'b100) ? ~(8'b0000_0001 << I) : 8'b0000_0000;

endmodule

DE2-115 開發以 Tri-State gate 74125/74126 為例(Verilog data flow modeling )

//Tirstate_Buffer_74126 74125

module Tirstate_Buffer_74126(SW, LEDR, LEDG , CLOCK_50 ,KEY,HEX0 ,HEX1 ,HEX2,HEX3 ,HEX4 ,HEX5 ,HEX6 ,HEX7 );

input [17:0] SW; // toggle switches

input [3:0] KEY; // Push bottom

input CLOCK_50; //Clock 27MHz , 50Mhz

output [17:0] LEDR; // red LEDS

output [8:0] LEDG; // green LEDs

output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7 ; //7-segment display

assign HEX0=7'b111_1111; //off 7-segment Display

assign HEX1=7'b111_1111;

assign HEX2=7'b111_1111; //off 7-segment Display

assign HEX3=7'b111_1111;

assign HEX4=7'b111_1111;

assign HEX5=7'b111_1111;

assign HEX6=7'b111_1111;

assign HEX7=7'b111_1111;

tri_buf_74126 u1(SW[0],LEDR[0],KEY[0]);

tri_buf_74126 u2(SW[2],LEDR[2],KEY[1]);

tri_buf_74125 u3(SW[4],LEDR[4],KEY[2]);

tri_buf_74125 u4(SW[6],LEDR[6],KEY[3]);

endmodule

module tri_buf_74126 (a,b,enable);

input a;

output b;

input enable;

wire b;

assign b = (enable) ? a : 1'bz;

endmodule

module tri_buf_74125 (a,b,enable);

input a;

output b;

input enable;

wire b;

assign b = (~enable) ? a : 1'bz;

endmodule

DE2-115 開發以 XOR gate 7486 為例(Verilog gate level & data flow modeling )

//7432 OR Gate

module gate_7486_XOR(SW,LEDR );

input [17:0] SW;

output [17:0] LEDR;

xor_gate(SW[17:0],LEDR[17:0]);

endmodule

//======================

//-- or_gate.v

//-- Component has an input (Din) and an output (Dout)

module xor_gate( Din, Dout );

input [17:0]Din;

output [17:0]Dout;

//-- Both the input and the output are "wires"

wire [17:0]Din;

wire [17:0]Dout;

//gate-level modeling

xor(Dout[0], Din[0], Din[1]);

xor (Dout[2], Din[2], Din[3]);

// Data flow modeling

assign Dout[4]= (Din[4] ^ Din[5]);

assign Dout[6]= (Din[6] ^ Din[7]);

assign Dout[8]= (Din[8] ^ Din[9]);

assign Dout[10]= (Din[10] ^ Din[11]);

assign Dout[12]= (Din[12] ^ Din[13]);

assign Dout[14]= (Din[14] ^ Din[15]);

assign Dout[16]= (Din[16] | Din[17]);

//behavioral modeling

endmodule

2021年3月25日星期四

DE2-115 開發以 8bit comparator (Verilog behavioral modeling )

module Comparator_8bit(SW, LEDR, LEDG , CLOCK_50 ,KEY,HEX0 ,HEX1 ,HEX2,HEX3 ,HEX4 ,HEX5 ,HEX6 ,HEX7 );

input [17:0] SW; // toggle switches

input [3:0] KEY; // Push bottom

input CLOCK_50; //Clock 27MHz , 50Mhz

output [17:0] LEDR; // red LEDS

output [8:0] LEDG; // green LEDs

output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7 ; //7-segment display

assign HEX0=7'b111_1111; //off 7-segment Display

assign HEX1=7'b111_1111;

assign HEX2=7'b111_1111; //off 7-segment Display

assign HEX3=7'b111_1111;

assign HEX4=7'b111_1111;

assign HEX5=7'b111_1111;

assign HEX6=7'b111_1111;

assign HEX7=7'b111_1111;

Comparator8Bit (SW[7:0],SW[15:8],LEDR[0],LEDR[1],LEDR[2]);

endmodule

module Comparator8Bit(

input[7:0] a,

input[7:0] b,

output eq,

output lt,

output gt);

wire[3:0] a1, a2, b1, b2;

wire eq1, eq2, lt1, lt2, gt1, gt2;

assign a1 = {a[3:0]};

assign a2 = {a[7:4]};

assign b1 = {b[3:0]};

assign b2 = {b[7:4]};

Comparator4Bit BC_1(a1, b1, eq1, lt1, gt1);

Comparator4Bit BC_2(a2, b2, eq2, lt2, gt2);

assign eq = (eq1 & eq2);

assign lt = (lt2 | (eq2 & lt1 ));

assign gt = (~lt & ~eq);

endmodule

module Comparator4Bit(

input[3:0] a,

input[3:0] b,

output eq,

output lt,

output gt);

assign eq = a == b;

assign lt = a < b;

assign gt = a > b;

endmodule

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2021年3月27日 星期六

2021年3月26日 星期五

2021年3月25日 星期四

2021年3月27日星期六

2021年3月26日星期五

2021年3月25日星期四