2014年11月22日星期六

漣波計數器（Ripple Counter）適用於DE2-70

漣波計數器（Ripple Counter）適用於DE2-70

計數器是能根據輸入脈衝而產生一連串預定順序狀態的暫存器，所以計數器也是由正反器所構成。一個四位元二進位漣波計數器是由ＪＫ正反器的補數運算所構成，每個正反器的輸出的都依序連到下一個正反器的Ck輸入，儲存最低有效位元的正反器所接受的是計數脈衝
。所有正反器的Ｊ與Ｋ兩輸入都恆接到邏輯１。

源自於http://www.electronics-tutorials.ws/counter/count_2.html

Asynchronous Counter

In the previous tutorial we saw that an Asynchronous counter can have 2n-1 possible counting states e.g. MOD-16 for a 4-bit counter, (0-15) making it ideal for use in Frequency Division. But it is also possible to use the basic asynchronous counter to construct special counters with counting states less than their maximum output number by forcing the counter to reset itself to zero at a pre-determined value producing a type of asynchronous counter that has truncated sequences. Then an n-bit counter that counts up to its maximum modulus (2n) is called a full sequence counter and a n-bit counter whose modulus is less than the maximum possible is called a truncated counter.

But why would we want to create an asynchronous truncated counter that is not a MOD-4, MOD-8, or some other modulus that is equal to the power of two. The answer is that we can by using combinational logic to take advantage of the asynchronous inputs on the flip-flop. If we take the modulo-16 asynchronous counter and modified it with additional logic gates it can be made to give a decade (divide-by-10) counter output for use in standard decimal counting and arithmetic circuits.

Such counters are generally referred to as Decade Counters. A decade counter requires resetting to zero when the output count reaches the decimal value of 10, ie. when DCBA = 1010 and to do this we need to feed this condition back to the reset input. A counter with a count sequence from binary "0000" (BCD = "0") through to "1001" (BCD = "9") is generally referred to as a BCD binary-coded-decimal counter because its ten state sequence is that of a BCD code but binary decade counters are more common.

Asynchronous Decade Counter

This type of asynchronous counter counts upwards on each leading edge of the input clock signal starting from "0000" until it reaches an output "1010" (decimal 10). Both outputs QB and QD are now equal to logic "1" and the output from the NAND gate changes state from logic "1" to a logic "0" level and whose output is also connected to the CLEAR (CLR) inputs of all the J-K Flip-flops.

This signal causes all of the Q outputs to be reset back to binary "0000" on the count of 10. Once QB andQD are both equal to logic "0" the output of the NAND gate returns back to a logic level "1" and the counter restarts again from "0000". We now have a decade or Modulo-10 counter.

Decade Counter Truth Table

Clock Count	Output bit Pattern				Decimal Value
Clock Count	QD	QC	QB	QA	Decimal Value
1	0	0	0	0	0
2	0	0	0	1	1
3	0	0	1	0	2
4	0	0	1	1	3
5	0	1	0	0	4
6	0	1	0	1	5
7	0	1	1	0	6
8	0	1	1	1	7
9	1	0	0	0	8
10	1	0	0	1	9
11	Counter Resets its Outputs back to Zero

Decade Counter Timing Diagram

Using the same idea of truncating counter output sequences, the above circuit could easily be adapted to other counting cycles be simply changing the connections to the AND gate. For example, a scale-of-twelve (modulo-12) can easily be made by simply taking the inputs to the AND gate from the outputs at "QC" and "QD", noting that the binary equivalent of 12 is "1100" and that output "QA" is the least significant bit (LSB).

Since the maximum modulus that can be implemented with n flip-flops is 2n, this means that when you are designing truncated asynchronous counters you should determine the lowest power of two that is greater than or equal to your desired modulus. For example, lets say you wish to count from 0 to 39, or mod-40. Then the highest number of flip-flops required would be six, n = 6 giving a maximum MOD of 64 as five flip-flops would only equal MOD-32.

Now suppose we wanted to build a "divide-by-128" counter for frequency division we would need to cascade seven flip-flops since 128 = 2⁷. Using dual flip-flops such as the 74LS74 we would still need four IC's to complete the circuit.

One easy alternative method would be to use two TTL 7493's as 4-bit ripple counter/dividers. Since 128 = 16 x 8, one 7493 could be configured as a "divide-by-16" counter and the other as a "divide-by-8" counter. The two IC's would be cascaded together to form a "divide-by-128" frequency divider as shown.

Of course standard IC asynchronous counters are available such as the TTL 74LS90 programmable ripple counter/divider which can be configured as a divide-by-2, divide-by-5 or any combination of both. The 74LS390 is a very flexible dual decade driver IC with a large number of "divide-by" combinations available ranging form divide-by-2, 4, 5, 10, 20, 25, 50, and 100.

// Ch08 cnt6.v

// 三位元漣波計數器

module cnt6(SW, LEDR, LEDG , CLOCK_27 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3 ,HEX4 );

input [17:0] SW; // toggle switches

input [3:0] KEY; // Push bottom

input CLOCK_27; //Clock 27MHz , 50Mhz

output [17:0] LEDR; // red LEDS

output [8:0] LEDG; // green LEDs

output [6:0] HEX0,HEX1,HEX2,HEX3 ,HEX4; //7-segment display

//set original program input , output

//module cnt6 (Clk,Clr,Q);

//input Clk,Clr; // 一位元輸入

//output [2:0] Q; // 三位元輸出

//reg [2:0] Q; // 宣告為暫存器資料

wire Clk,Clr; // 一位元輸入

reg [3:0] Q; // 宣告為暫存器資料

wire [7:0] segout0; //HEX 0

assign Clk=KEY[0];

assign Clr=KEY[1];

assign LEDG[1:0]=KEY[1:0];

// 上緣觸發時脈, 上緣同步清除, T 型正反器

always@ (negedge Clk or negedge Clr) // 時脈為上緣觸發 Clk

if (!Clr) Q[0] = 0;

else Q[0] = ~Q[0];

always@ (negedge Q[0] or negedge Clr) // 時脈為下緣觸發 Q[0]

if (!Clr) Q[1] = 0;

else Q[1] = ~Q[1];

always@ (negedge Q[1] or negedge Clr) // 時脈為下緣觸發 Q[1]

if (!Clr) Q[2] = 0;

else Q[2] = ~Q[2];

always@ (negedge Q[2] or negedge Clr) // 時脈為下緣觸發 Q[1]

if (!Clr) Q[3] = 0;

else Q[3] = ~Q[3];

_7seg UUT0(.hex(Q),

.seg(segout0));

assign HEX0=segout0[6:0];

assign LEDG[7:4]=Q;

endmodule

//-----------------------------------------

//Common-cathod seven segment display

//using case.....endcase statement

//Filename : sevenseg_case.v

//-----------------------------------------

module _7seg(hex , seg);

input [3:0] hex;

output [7:0] seg;

reg [7:0] seg;

// segment encoding

// 0

// ---

// 5 | | 1

// --- <- 6

// 4 | | 2

// ---

// 3

always @(hex)

begin

case (hex)

// Dot point is always disable

4'b0001 : seg = 8'b11111001; //1 = F9H

4'b0010 : seg = 8'b10100100; //2 = A4H

4'b0011 : seg = 8'b10110000; //3 = B0H

4'b0100 : seg = 8'b10011001; //4 = 99H

4'b0101 : seg = 8'b10010010; //5 = 92H

4'b0110 : seg = 8'b10000010; //6 = 82H

4'b0111 : seg = 8'b11111000; //7 = F8H

4'b1000 : seg = 8'b10000000; //8 = 80H

4'b1001 : seg = 8'b10010000; //9 = 90H

4'b1010 : seg = 8'b10001000; //A = 88H

4'b1011 : seg = 8'b10000011; //b = 83H

4'b1100 : seg = 8'b11000110; //C = C6H

4'b1101 : seg = 8'b10100001; //d = A1H

4'b1110 : seg = 8'b10000110; //E = 86H

4'b1111 : seg = 8'b10001110; //F = 8EH

default : seg = 8'b11000000; //0 = C0H

endcase

end

endmodule

P7-3 左右移3bit 乘法/除法器適用於DE2-70

P7-3 左右移3bit 乘法/除法器適用於DE2-70

//-----------------------------------------------------------
//Shift left/right with 3 bits for a multiplier/divider by 8
//filename : shift_test.v
//----------------------------------------------------------
module shift3(SW, LEDR, LEDG , CLOCK_27 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3 );

input [17:0] SW; // toggle switches
input [7:0] KEY; // Push bottom
input CLOCK_27; //Clock 27MHz , 50Mhz

output [17:0] LEDR; // red LEDS
output [8:0] LEDG; // green LEDs

output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display


//set original program input , output

//(indata, qout, mout);

//output [7:0] qout; //quotient output
//output [7:0] mout; //product output
//input [7:0] indata; //input data

wire [7:0]indata ;
wire left_right ;
reg [7:0] shift_out;


//parameter sh_bit = 3; //define the number of bits for shifting
//parameter left =1;
//parameter right = 0;

assign left_right=SW[17];
assign indata=SW[7:0];
assign LEDR[7:0]=SW[7:0];

always @ (indata or left_right)
begin
shift_out = mult_div_8(left_right, indata); // multiplier function call

end

assign LEDG[7:0] = shift_out ;


//Function mult_div_8
function [7:0] mult_div_8;
input fcn_left;
input [7:0] fcn_in;
begin
mult_div_8 = (fcn_left == 1)? (fcn_in << 3) : (fcn_in >> 3);
end
endfunction

endmodule

Serial-in, parallel-out shift register

A serial-in/parallel-out shift register is similar to the serial-in/ serial-out shift register in that it shifts data into internal storage elements and shifts data out at the serial-out, data-out, pin. It is different in that it makes all the internal stages available as outputs. Therefore, a serial-in/parallel-out shift register converts data from serial format to parallel format. If four data bits are shifted in by four clock pulses via a single wire at data-in, below, the data becomes available simultaneously on the four Outputs Q_A to Q_D after the fourth clock pulse.

The practical application of the serial-in/parallel-out shift register is to convert data from serial format on a single wire to parallel format on multiple wires. Perhaps, we will illuminate four LEDs (Light Emitting Diodes) with the four outputs (Q_A Q_B Q_C Q_D ).

The above details of the serial-in/parallel-out shift register are fairly simple. It looks like a serial-in/ serial-out shift register with taps added to each stage output. Serial data shifts in at SI (Serial Input). After a number of clocks equal to the number of stages, the first data bit in appears at SO (Q_D) in the above figure. In general, there is no SO pin. The last stage (Q_D above) serves as SO and is cascaded to the next package if it exists.

If a serial-in/parallel-out shift register is so similar to a serial-in/ serial-out shift register, why do manufacturers bother to offer both types? Why not just offer the serial-in/parallel-out shift register? They actually only offer the serial-in/parallel-out shift register, as long as it has no more than 8-bits. Note that serial-in/ serial-out shift registers come in bigger than 8-bit lengths of 18 to to 64-bits. It is not practical to offer a 64-bit serial-in/parallel-out shift register requiring that many output pins. See waveforms below for above shift register.

The shift register has been cleared prior to any data by CLR', an active low signal, which clears all type D Flip-Flops within the shift register. Note the serial data 1011 pattern presented at the SI input. This data is synchronized with the clock CLK. This would be the case if it is being shifted in from something like another shift register, for example, a parallel-in/ serial-out shift register (not shown here). On the first clock at t1, the data 1 at SI is shifted from D to Q of the first shift register stage. After t2 this first data bit is at Q_B. After t3 it is at Q_C. After t4 it is at Q_D. Four clock pulses have shifted the first data bit all the way to the last stage Q_D. The second data bit a 0 is at Q_C after the 4th clock. The third data bit a 1 is at Q_B. The fourth data bit another 1 is at Q_A. Thus, the serial data input pattern 1011 is contained in (Q_D Q_C Q_B Q_A). It is now available on the four outputs.

It will available on the four outputs from just after clock t₄ to just before t₅. This parallel data must be used or stored between these two times, or it will be lost due to shifting out the Q_D stage on following clocks t₅to t₈ as shown above.

Serial-in/ parallel-out devices

Let's take a closer look at Serial-in/ parallel-out shift registers available as integrated circuits, courtesy of Texas Instruments. For complete device data sheets follow the links.

SN74ALS164A serial-in/ parallel-out 8-bit shift register
[*]
SN74AHC594 serial-in/ parallel-out 8-bit shift register with output register

[*]
SN74AHC595 serial-in/ parallel-out 8-bit shift register with output register
[*]
CD4094 serial-in/ parallel-out 8-bit shift register with output register
[*]

[*]

The 74ALS164A is almost identical to our prior diagram with the exception of the two serial inputs A and B. The unused input should be pulled high to enable the other input. We do not show all the stages above. However, all the outputs are shown on the ANSI symbol below, along with the pin numbers.

The CLK input to the control section of the above ANSI symbol has two internal functions C1, control of anything with a prefix of 1. This would be clocking in of data at 1D. The second function, the arrow after after the slash (/) is right (down) shifting of data within the shift register. The eight outputs are available to the right of the eight registers below the control section. The first stage is wider than the others to accommodate the A&B input.

The above internal logic diagram is adapted from the TI (Texas Instruments) data sheet for the 74AHC594. The type "D" FFs in the top row comprise a serial-in/ parallel-out shift register. This section works like the previously described devices. The outputs (Q_A' Q_B' to Q_H' ) of the shift register half of the device feed the type "D" FFs in the lower half in parallel. Q_H' (pin 9) is shifted out to any optional cascaded device package.

A single positive clock edge at RCLK will transfer the data from D to Q of the lower FFs. All 8-bits transfer in parallel to the output register (a collection of storage elements). The purpose of the output register is to maintain a constant data output while new data is being shifted into the upper shift register section. This is necessary if the outputs drive relays, valves, motors, solenoids, horns, or buzzers. This feature may not be necessary when driving LEDs as long as flicker during shifting is not a problem.

Note that the 74AHC594 has separate clocks for the shift register (SRCLK) and the output register ( RCLK). Also, the shifter may be cleared by SRCLR and, the output register by RCLR. It desirable to put the outputs in a known state at power-on, in particular, if driving relays, motors, etc. The waveforms below illustrate shifting and latching of data.

The above waveforms show shifting of 4-bits of data into the first four stages of 74AHC594, then the parallel transfer to the output register. In actual fact, the 74AHC594 is an 8-bit shift register, and it would take 8-clocks to shift in 8-bits of data, which would be the normal mode of operation. However, the 4-bits we show saves space and adequately illustrates the operation.

We clear the shift register half a clock prior to t₀ with SRCLR'=0. SRCLR' must be released back high prior to shifting. Just prior to t₀ the output register is cleared by RCLR'=0. It, too, is released ( RCLR'=1).

Serial data 1011 is presented at the SI pin between clocks t₀ and t₄. It is shifted in by clocks t₁ t₂ t₃ t₄appearing at internal shift stages Q_A' Q_B' Q_C' Q_D' . This data is present at these stages between t₄ and t₅. After t₅ the desired data (1011) will be unavailable on these internal shifter stages.

Between t₄ and t₅ we apply a positive going RCLK transferring data 1011 to register outputs Q_A Q_B Q_C Q_D. This data will be frozen here as more data (0s) shifts in during the succeeding SRCLKs (t₅ to t₈). There will not be a change in data here until another RCLK is applied.

The 74AHC595 is identical to the '594 except that the RCLR' is replaced by an OE' enabling a tri-state buffer at the output of each of the eight output register bits. Though the output register cannot be cleared, the outputs may be disconnected by OE'=1. This would allow external pull-up or pull-down resistors to force any relay, solenoid, or valve drivers to a known state during a system power-up. Once the system is powered-up and, say, a microprocessor has shifted and latched data into the '595, the output enable could be asserted (OE'=0) to drive the relays, solenoids, and valves with valid data, but, not before that time.

Above are the proposed ANSI symbols for these devices. C3 clocks data into the serial input (external SER) as indicate by the 3 prefix of 2,3D. The arrow after C3/ indicates shifting right (down) of the shift register, the 8-stages to the left of the '595symbol below the control section. The 2 prefix of 2,3D and 2D indicates that these stages can be reset by R2 (external SRCLR').

The 1 prefix of 1,4D on the '594 indicates that R1 (external RCLR') may reset the output register, which is to the right of the shift register section. The '595, which has an EN at external OE' cannot reset the output register. But, the EN enables tristate (inverted triangle) output buffers. The right pointing triangle of both the '594 and'595 indicates internal buffering. Both the '594 and'595 output registers are clocked by C4 as indicated by 4 of 1,4D and 4D respectively.

The CD4094B is a 3 to 15V_DC capable latching shift register alternative to the previous 74AHC594 devices.CLOCK, C1, shifts data in at SERIAL IN as implied by the 1 prefix of 1D. It is also the clock of the right shifting shift register (left half of the symbol body) as indicated by the /(right-arrow) of C1/(arrow) at theCLOCK input.

STROBE, C2 is the clock for the 8-bit output register to the right of the symbol body. The 2 of 2D indicates that C2 is the clock for the output register. The inverted triangle in the output latch indicates that the output is tristated, being enabled by EN3. The 3 preceding the inverted triangle and the 3 of EN3 are often omitted, as any enable (EN) is understood to control the tristate outputs.

Q_S and Q_S' are non-latched outputs of the shift register stage. Q_S could be cascaded to SERIAL IN of a succeeding device.

Practical applications

A real-world application of the serial-in/ parallel-out shift register is to output data from a microprocessor to a remote panel indicator. Or, another remote output device which accepts serial format data.

The figure "Alarm with remote key pad" is repeated here from the parallel-in/ serial-out section with the addition of the remote display. Thus, we can display, for example, the status of the alarm loops connected to the main alarm box. If the Alarm detects an open window, it can send serial data to the remote display to let us know. Both the keypad and the display would likely be contained within the same remote enclosure, separate from the main alarm box. However, we will only look at the display panel in this section.

If the display were on the same board as the Alarm, we could just run eight wires to the eight LEDs along with two wires for power and ground. These eight wires are much less desirable on a long run to a remote panel. Using shift registers, we only need to run five wires- clock, serial data, a strobe, power, and ground. If the panel were just a few inches away from the main board, it might still be desirable to cut down on the number of wires in a connecting cable to improve reliability. Also, we sometimes use up most of the available pins on a microprocessor and need to use serial techniques to expand the number of outputs. Some integrated circuit output devices, such as Digital to Analog converters contain serial-in/ parallel-out shift registers to receive data from microprocessors. The techniques illustrated here are applicable to those parts.

We have chosen the 74AHC594 serial-in/ parallel-out shift register with output register; though, it requires an extra pin, RCLK, to parallel load the shifted-in data to the output pins. This extra pin prevents the outputs from changing while data is shifting in. This is not much of a problem for LEDs. But, it would be a problem if driving relays, valves, motors, etc.

Code executed within the microprocessor would start with 8-bits of data to be output. One bit would be output on the "Serial data out" pin, driving SER of the remote 74AHC594. Next, the microprocessor generates a low to high transition on "Shift clock", driving SRCLK of the '595 shift register. This positive clock shifts the data bit at SER from "D" to "Q" of the first shift register stage. This has no effect on the Q_ALED at this time because of the internal 8-bit output register between the shift register and the output pins (Q_A to Q_H). Finally, "Shift clock" is pulled back low by the microprocessor. This completes the shifting of one bit into the '595.

The above procedure is repeated seven more times to complete the shifting of 8-bits of data from the microprocessor into the 74AHC594 serial-in/ parallel-out shift register. To transfer the 8-bits of data within the internal '595 shift register to the output requires that the microprocessor generate a low to high transition on RCLK, the output register clock. This applies new data to the LEDs. The RCLK needs to be pulled back low in anticipation of the next 8-bit transfer of data.

The data present at the output of the '595 will remain until the process in the above two paragraphs is repeated for a new 8-bits of data. In particular, new data can be shifted into the '595 internal shift register without affecting the LEDs. The LEDs will only be updated with new data with the application of the RCLKrising edge.

What if we need to drive more than eight LEDs? Simply cascade another 74AHC594 SER pin to the Q_H' of the existing shifter. Parallel the SRCLK and RCLK pins. The microprocessor would need to transfer 16-bits of data with 16-clocks before generating an RCLK feeding both devices.

The discrete LED indicators, which we show, could be 7-segment LEDs. Though, there are LSI (Large Scale Integration) devices capable of driving several 7-segment digits. This device accepts data from a microprocessor in a serial format, driving more LED segments than it has pins by by multiplexing the LEDs. For example, see link below for MAX6955

[*]

源自http://bawankule.com/verilogfaq/page2.html

Verilog FAQ Version 09/05: September 2005

Part 1:

Introduction :

 What is Verilog?

Verilog HDL is a hardware description language used to design and document electronic systems. Verilog HDL allows designers to design at various levels of abstraction. It is the most widely used HDL with a user community of more than 50,000 active designers.

A brief history

Verilog HDL originated at Automated Integrated Design Systems (later renamed as Gateway Design Automation) in 1985. The company was privately held at that time by Dr. Prabhu Goel, the inventor of the PODEM test generation algorithm. Verilog HDL was designed by Phil Moorby, who was later to become the Chief Designer for Verilog-XL and the first Corporate Fellow at Cadence Design Systems. Gateway Design Automation grew rapidly with the success of Verilog-XL and was finally acquired by Cadence Design Systems, San Jose, CA in 1989.
Verilog was invented as simulation language. Use of Verilog for synthesis was a complete afterthought
Cadence Design Systems decided to open the language to the public in 1990, and thus OVI (Open Verilog International) was born. Till that time, Verilog HDL was a proprietary language, being the property of Cadence Design Systems. When OVI was formed in 1991, a number of small companies began working on Verilog simulators. The first of these came to market in 1992, and now there are mature Verilog simulators available from several sources.
As a result, the Verilog market has grown substantially. The market for Verilog related tools in 1994 was well over $75m, making it the most commercially significant hardware description language on the market.
An IEEE working group was established in 1993 under the Design Automation Sub-Committee to produce the IEEE Verilog standard 1364. Verilog became IEEE Standard 1364 in 1995.
The Verilog Standard was revised in 2001 and it became IEEE Standard 1364-2001
Verilog is evolutionary language. It is growing to cater needs of system designers, verification engineers too. Extensions to existing Verilog language are proposed by Accelera. Accellera was formed in 2000 through the unification of Open Verilog International and VHDL International.

Visit Accelera site to download System Verilog 3.1a LRM.

comp.lang.verilog

comp.lang.verilog is an unmoderated newsgroup which passed its vote for creation by 332:9 as reported in news.announce.newgroups on 12 Dec 1991. The charter, culled from the call for votes:
The USENET group is intended at providing a forum for the discussion of topics specific to Verilog, PLI (programming language interface), SDF (Standard delay file format), Synthesis guidelines, compliance and Verilog modeling. It will also provide users with an ability to share Verilog/PLI utilities. Users can also use the forum to discuss any Verilog related issues proposed by Open Verilog International and its organizational and technical committees.

Participating in discussions on comp.lang.verilog

- Deja News used to provide free usenet. Now it is bought by Google and new incarnation is available athttp://groups.google.com/

Link to comp.lang.verilog is at
http://groups.google.com/groups? hl=en&lr=&safe=off&group=comp.lang.verilog
You can read as well as post the messages.

- http://www.news2mail.com/ You can provide your email address to get postings sent to your email address.

- Your own ISP. Most ISP (Internet service providers) provide news service. You can configure your Netscape, Outlook express or other news readers like Forte Agent to
read available news groups available with the server.

EDA Industry Working Groups

The archives and more information about the Electronic Design Automation (EDA) and Electronic Computer Aided Design (ECAD) related Industry working groups is kept at http://www.eda.org/
Some relevant groups are

Open Verilog International (OVI)
Verilog Synthesis Subset Working Group (IEEE PAR 1364.1)
Verilog Analog Mixed Signal (verilog-ams) Working Group
Standard Delay Format (SDF) Study Group (IEEE PAR 1497)
Advanced Library Format (alf) Working Group
Accellera Design Constraints Working Group
Verilog Formal Verification (vfv) Working Group
[Integrated Circuit] Architectural Language (arch) Working Group

Conference Proceedings archives

Archive of proceeding from various conferences like DAC, FPGA conferences is kep here.http://www.sigda.org/Archives/ProceedingArchives/index.html

General Topics:

Verilog BNF

Verilog BNF lists the formal syntax of Verilog language as defined in Verilog Language Reference Manual.
http://www.verilog.com/VerilogBNF.html

Editors which support Verilog

GNU Xemacs: It is available from http://www.xemacs.org GNU Emacs on Windows NT and Windows 95/98

http://www.gnu.org/software/emacs/windows/ntemacs.html

Use Emacs / Xemacs with Verilog mode. Michael McNamara , President, Surefire Verification Inc. maintains Verilog Mode for emacs. You can download it from its own web pagehttp://www.verilog.com/verilog-mode.html
It has installation guide on the page. If you have any problems with the file, you can submit a bug report by sending mail to mac@surefirev.com

Source Navigator for Verilog: Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many verilog files. It parses verilog code into a database that can be used to navigate files, trace connectivity, and find modules and signals in the design. It can even parse your files as you edit so you don't launch those long compile scripts only to end up with a syntax error after 5 minues of compiling.
Downloads are available for Solaris and Linux.
More Information : http://snverilog.sourceforge.net/
Downloads : http://sourceforge.net/projects/snverilog/
The Prism Editor: is an 'environmentally friendly' editor designed for Windows NT/95/98. No matter what type of files you edit on a daily basis, the editor can incorporate them into a productive system.

This Shareware editor is available with extensions for Verilog, VHDL, C, ABEL, PALASM, HTML, Synopsys Script File, Synplify TCL, UCF, Synopsys Log File and Error files
http://www.iol.ie/~dmurray/Prism/Prism_Editor.html

Use Crisp editor with verilog tags and print from it. More info / downloads are available fromhttp://www.crisp.com/

Use vim (vi improved). xvim is its GUI version. Download from http://www.vim.org/ It supports almost every verilog simulation platform, such as Linux, Solaris, Hp, Sun OS, and Windows.

ed from GetSoft http://www.getsoft.com/

For pretty printing one can use above mentioned editors or

standalone a2ps with Verilog extension. You can get information and files on web. for examplehttp://www.gnu.org/software/a2ps/a2ps.html Verilog is listed in Known Languages section.
GNU enscript from ftp://prep.ai.mit.edu/pub/gnu/enscript/

Verilog to HTML converter

There are two converters available now.
1. Costas Calamvokis developed Verilog to HTML converter with lots of features. His v2html perl script is a new (free!) way of viewing your verilog designs. It converts your verilog files into html with all of the keywords, comments and strings prettily colored so they stand out. More usefully, it links various design elements so that you can click on the name and see what it is. Once you have run v2html on your design you can view the files directly in your browser, or you can put them on a web server for other people to see.
Visit and download his scripts from http://www.burbleland.com/v2html/v2html.html

2. Venkateswarlu Talapaneni of Comit Systems Inc has designed Verilog to HTML converter.
He says ...
Design documents are extensively getting published on web. There are not emacs mode type script facilities available to format verilog files for web publishing. I made first attempt to solve this problem. You can use this perl script to convert your verilog file to html.
In this implementation

Comments are given green color
keyword are made bold.

Please send your experiences , comments to me (neni@comit.com) to make this utility more useful.Usage
vlog2html <vlog_file> [<html_file>]

vlog_file     Name of the Verilog file that is to be converted
html_file     Name of the output HTML file. Default is the name of the
                                     vlog_file, with .v substituted by .html
Download

vlog2html perl script
demo.v before conversion
demo.html shown below

vgrind def file
It is available in the verilog archives as: verilog-vgrind-def.Z

Verilog / ASIC / EDA related magazines.

Here are links to some of the available magazines.

Integrated System Design (discontinued)	Archives Available here.
Chip Design Magazine	http://www.chipdesignmag.com/
EDN Magazine	http://www.ednmag.com
EE Times	http://www.eet.com/
Cadence Plugged In Magazine	http://www.cadence.com

Related Web sites?

Here are some links to Verilog related sites:
Cadmazing's DA-Related Information on the Web
http://www.cadmazing.com/cadmazing/pages/da.html
Electronic Design Automation Companies
http://www.edac.org
IVC (International Verilog Conference) and VHDL International Users Forum(VIUF)
http://www.hdlcon.org
DAC (Design Automation Conference)
http://www.dac.com
Programmable Logic Jump Station
http://www.optimagic.com
Veripool : Public Domain Verilog Resources
http://www.ultranet.com/~wsnyder/veripool/

Conferences and Paper contests

Design, Verification Conference and ExhibitionDate: February 22-24, 2006
Venue: Doubletree Hotel, San Jose, CA, USAMore Information : http://www.dvcon.com/
40th Design Automation Conference
Date : July 24-26, 2006
Venue : Moscone Center, San Francisco, CA, USA
More Information: http://www.dac.com/
The International Conference on Computer Aided Design, ICCAD-99
Date: November 06-10, 2005
Venue: DoubleTree Hotel, San Jose, CA
More Information: http://www.iccad.com/
ACM International Symposium on Physical Design
Date: April 9-12, 2006
Venue: San Jose, CA
More Information: http://www.ispd.cc/

Synopsys User Group
More Information: http://www.snug-universal.org/
This site also has synthesis, project management, low power design etc. related SNUG papers.
Note: You need to have solve-it id from Synopsys to access them.
To see other EDA related conferences visit EE Times Calendar of Trade shows and Conferences.

Books and Reference material on Verilog

	Verilog HDL : A Guide to Digital Design and Synthesisby Samir Palnitkar Bk&Cd-Rom Edition Hardcover, 396 pages Price : $65.00 Published by Prentice Hall Publication date: March 1996 Dimensions (in inches): 9.48 x 7.13 x .98 ISBN: 0134516753 (More information)
	HDL Chip Design : A Practical guide for Designing, Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilogby Douglas J. Smith price : $65.00 Publication date: June 1st 1996 Large format (8.5 x 11) inches hardcover 464 pages ISBN: 0-9651934-3-8
	Real Chip Design and Verification Using Verilog and VHDL by Ben Cohen Price: $80 ISBN 0-9705394-2-8 VhdlCohen Publishing, November 2001, 420 pages. (More Information)
	Verilog HDL Synthesis, A Practical Primerby J. Bhasker 236 pages; soft cover; US$49.95 (Quantity discounts) ISBN 0-9650391-5-3 Star Galaxy Publishing (More Information)
	A Verilog HDL Primerby J. Bhasker Bk&Hardcover; Price : US$59.95 (Quantity discounts) Published by Star Galaxy Press. (More information) ISBN: 0-9656277-4-8
	Verilog Quickstart, 3rd Editionby James M. Lee Hardcover Published by Kluwer Academic Publishers ISBN: 0-7923-7672-2 (More Information) Price: $98.00
	Verilog Designer's Libraryby Bob Zeidman Prentice Hall; ISBN: 0130811548 Hardcover - 416 pages Bk&Cd Rom edition (July 1999) Price: $75.00 (More Information)
	The Verilog Hardware Description Language by Thomas, D . E . / Moorby, Philip R . Fourth Edition Published by Kluwer Academic Publishers Date Published: 05/1998 ISBN: 0792381661 Price: $98.00 Hardcover; 354 Pages

Digital Design With Verilog HDL (Design Automation Series)by Eliezer Sternheim, Rajvir Singh, Yatin Trivedi
Paperback Price: $69.50
Published by Chapman & Hall
Publication date: May 1991
ISBN: 0962748803
"Modeling, Synthesis and Rapid Prototyping with the Verilog HDL"
by Michael D. Ciletti.
Prentice Hall; ISBN: 0139773983 Price: $100.00
Hardcover - 727 pages Bk&Cd Rom edition (August 1999)

IEEE Std 1364-1995 : IEEE Standard Hardware Description Language based on the Verilog Hardware Description Language
Published by the IEEE, Inc., 345 East 47th Street, New York, NY 10017, USA
ISBN 1-55937-727-5 (More Info)
Successful ASIC Design the First Time Through
by John P. Huber, Mark W. Rosneck
Hardcover Price: $49.95
Published by Van Nostrand Reinhold (Short Disc)
Publication date: May 1991
ISBN: 0442003129

OPEN VERILOG INTERNATIONAL (OVI) REFERENCE MATERIALS
OVI is the organization charged with Verilog standardization and language enhancements.
For the following publications contact Lynn Horobin at the OVI office.
Open Verilog International
Lynn Horobin
15466 Los Gatos Blvd., Suite 109-071
Los Gatos, CA 95032
Phone: (408) 353-8899 -- FAX: (408) 353-8869
e-mail: ovi@netcom.com
(1) "LANGUAGE REFERENCE MANUAL" (LRM), Version 2.0*
- $100 per copy, plus local sales tax
(2) "PROGRAMMING LANGUAGE INTERFACE" (PLI), Version 2.0*
- $150 per copy, plus local sales tax
(3) "STANDARD DELAY FILE FORMAT MANUAL" (SDF), Version 2.0*
- $100 per copy, plus local sales tax

Books on HDL Verification

	"Writing testbenches: Functional Verification of HDL Models" by Janick BergeronCover price: $US98. ISBN 0-7923-7766-4 (More Information)
	"Principles of Verifiable RTL Design" by Lionel Bening and Harry FosterCover price: $US98. ISBN 0-7923-7788-5 (More Information)

Free Stuff :

Free Verilog simulator

There are three free Verilog simulators available with limited capabilities:
Online Simulator Icarus Verilog: It is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists in the desired format.
The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standardIEEE Std 1364-2000. The standard proper is due to be release towards the middle of the year 2000. This is a fairly large and complex standard, so it will take some time for it to get there. More information and downloads are available at http://www.icarus.com/eda/verilog/index.htmlThe main compiler is written by Stephen Williams
Precompiled Windows binaries are at
ftp://icarus.com/pub/eda/verilog/v0.7/Windows/
ASICDesign Info page has first of its kind online simulator. It has a limitation of 30sec run time
per job. Its primary purpose is for some one interested in verilog to learn by using it without installing and learning about the tool.
SILOS III from Simucad.
SILOS III's high performance logic and fault simulation environment supports the Verilog Hardware Description Language for simulation at multiple levels of abstraction. The Environment's state-of-the-art architecture incorporates an exclusive integrated / interactive multi-tasking graphical debugging environment that provides unsurpassed accuracy and outstanding performance.
GPL CVer from Pragmatic-C

GPL Cver is a Verilog HDL simulator that is released under the GNU General Public License. GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also implements some of the 2001 P1364 standard features including all three PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language Reference Manual (LRM).
VeriLogger from SynaptiCAD
VeriLogger is a free an IEEE-1364 compliant Verilog simulator. VeriLogger combines many of the best ideas from modern programming IDEs and SynaptiCAD's timing diagram editing environment to created an interactive simulator with graphical stimulus generation. VeriLogger has a powerful hierarchical browser that displays the structural relationships of the modules. It also includes waveform viewing, single step debugging, point-and-click breakpoints, graphical and console execution (command line version). Download a free evaluation version of VeriLogger Pro from
http://www.syncad.com/
SMASH from Dolphin Integration
Dolphin Integration offers evaluation version of SMASH simulator which is a mixed signal,multi-level simulator.SMASH implements the full Verilog-HDL IEEE standard. The implementation is based on the OVI Reference Manuals.
SMASH supports the SDF (Standard Delay File) format, to allow back annotation from layout tools.
This evaluation version is a full featured system (they will not allow you to compile new behavioral models though). They will not handle large circuits. The number of analog nodes is limited to 25, and the number of digital nodes is limited to 50.
http://www.dolphin.fr/

VBS: VBS stands for Verilog Behavioral Simulator. Jimen Ching wrote this for his senior design project at the University of Hawaii. Since then, he has extensively added more features.
http://www.flex.com/~jching/
Old Verwell simulator for Linux is available at
ftp://ftp.syncad.com/pub/synapticad/current/vlogcmd-linux-glibc.tar.gz

Free Simulation Waveform Viewer

There are 4 free Verilog waveform viewers:
Icarus Verilog Interactive (IVI for short) is an interactive front-end to the superb verilog compiler/simulator written by Stephen Williams (found at www.icarus.com).
Icarus also works with a waveform viewer, such as GTKwave
http://www.linux-workshop.com/bybell/ver/wave/wave.html
http://www.cs.man.ac.uk/apt/tools/gtkwave/index.html
There are prepackaged RPMS for Linux here:
ftp://ftp.icarus.com/pub/eda/gtkwave/

Precompiled Windows Version:
http://www.geocities.com/SiliconValley/Campus/3216/GTKWave/gtkwave-win32.html
VeriLogger Pro from SynaptiCAD will handle small Verilog files without a license. You can download it from http://www.syncad.com
Dinotrace is a X-11 waveform viewer which understands Verilog Value Change Dumps, ASCII, and other trace formats. It allows placing cursors, highlighting signals, searching, printing, and other capabilities superior to many commercial waveform viewers.
Dinotrace is made available by Wilson Snyder
http://www.veripool.com/dinotrace/

Free Verilog Design Rule Checker

Design Rule checkers / linting tools are used for

Finding out non-synthesizable constructs and potential mismatches in RTL and netlist simulations.
Reviewing Verilog code for company-wide reuse / consistency in style.
Making sure that code matches with established standards of reuse, for example Reuse Methodology manual from Synopsys/Mentor Graphics.

TransEDA offers an online demo of their HDL checker called VN-Check.
This service is free. Registration required.

Free Timing Analyzer

The TimingAnalyzer can be used to draw and edit timing diagrams and check for timing problems in digital systems. The diagrams can be included in word processing documents, printed, and saved as JPG or GIF image files. The signal diagrams are saved as text files so they are easy to modify or distribute.
Visit Dan Fabrizio's site http://www.timinganalyzer.net/ to learn more and download. Currently, the program is in a beta testing. While it is in beta testing anyone can use the program for free.

Free VHDL to Verilog Translator

A VHDL to Verilog RTL translator is avaliable under GPL.
http://www.ocean-logic.com/downloads.htm

The tool supports a limited but useful subset of VHDL and it has been tested on company's JPEG and triple DES cores.

Free Verilog to C++ / System C Translator

Verilator from Veripool is a Verilog to C translator. Verilator is a Experimental program. It converts Synthesizable Verilog (not test-bench code!) into C++ or SystemC code.

Free Verilog Code Coverage Tool

Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test.
http://covered.sourceforge.net/

Free Verilog LRM

An experimental Verilog LRM is available from http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Verilog/Verilog.htm
This material is an experimental project to link ASICs... the book with the IEEE Verilog(TM) HDL Language Reference Manual. The Verilog(TM) HDL LRM is copyright material. This project is not intended for public distribution.

Free Verilog quick reference card

On-line Verilog HDL Quick Reference Guide by Stuart Sutherland.
A postscript quick reference card has been donated by Rajeev Madhavan.

ref.pdf

Comit Systems, Inc has published Verilog Quick Reference Card in ISD magazine September 1997. It is available free of charge. Email your postal address to info@comit.com
For engineers using Verilog & VHDL to design ASICs, HDL Quick Reference manuals have just been released for both languages on Pocket-PC, Win-CE and Palm-OS by Comit Systems, Inc. of Santa Clara, CA.

The Quick PDA References are available for FREE download on the
company's website at http://www.comit.com/freestuff/freestuffhhqrc.html
Verilog Quick Reference card from Qualis Design

Free Verilog Tutorials
There are two quality interactive tutorials available on web currently.

Doulos HDL Associates offers Verilog HDL - Entry Edition free. It is Computer Based Multimedia Interactive Training. It is not a demonstrator but a practical introduction to Verilog and synthesis to get you up and running with Verilog.
It is currently available absolutely free from Doulos and can be downloaded directly from the web.
http://www.doulos.com/

ALDEC, Inc.
EVITA Verilog is available at http://www.aldec.com at no cost. It includes a complete Verilog reference guide with design samples and interactive Verilog tutorial. EVITA Verilog is aimed at hardware designers who have little or no Verilog experience and want to start getting involved with HDL based designs.

Free Verilog Obfuscator

Sometimes you want to ship your Verilog code without giving away your intellectual property. The simplest way to do is obfuscate it. You can find such obfuscater at http://www.eda-utilities.com/

Public domain Verilog preprocessor

Himanshu M. Thaker has written a Verilog Preprocessor which supports "generate" like statements known from VHDL. It is available from SureFire Verification Inc site.
http://www.surefirev.com/vpp/

訂閱：文章 (Atom)

2014年11月22日 星期六