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2021年4月4日星期日

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計D Flip Flop為例(TestBench平台)

module d_flip_flop_edge_triggered(Q, Qn, C, D);

output Q;

output Qn;

input C;

input D;

wire Cn; // Control input to the D latch.

wire Cnn; // Control input to the SR latch.

wire DQ; // Output from the D latch, input to the gated SR latch.

wire DQn; // Output from the D latch, input to the gated SR latch.

not(Cn, C);

not(Cnn, Cn);

d_latch dl(DQ, DQn, Cn, D);

sr_latch_gated sr(Q, Qn, Cnn, DQ, DQn);

endmodule // d_flip_flop_edge_triggered

module d_latch(Q, Qn, G, D);

output Q;

output Qn;

input G;

input D;

wire Dn;

wire D1;

wire Dn1;

not(Dn, D);

and(D1, G, D);

and(Dn1, G, Dn);

nor(Qn, D1, Q);

nor(Q, Dn1, Qn);

endmodule // d_latch

module sr_latch_gated(Q, Qn, G, S, R);

output Q;

output Qn;

input G;

input S;

input R;

wire S1;

wire R1;

and(S1, G, S);

and(R1, G, R);

nor(Qn, S1, Q);

nor(Q, R1, Qn);

endmodule // sr_latch_gated

`timescale 10ns/10ps

module D_FlipFlop_tb;

wire q;

wire qn;

reg ck;

reg din;

d_flip_flop_edge_triggered DUT(

.Q(q),

.Qn(qn),

.C(ck),

.D(din)

);

initial begin

ck=1'b0;din=1'b0;

#500 $stop;

end

always begin

#50 ck=~ck;

end

always begin

#100 din=~din;

end

endmodule

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計D Flip Flop為例(UpLoad to FPGA開發平台)

module DE2_115 (SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,HEX4 ,HEX5 ,HEX6,HEX7, GPIO );
input [17:0] SW; // toggle switches
input [7:0] KEY; // Push bottom
input CLOCK_50; //Clock 27MHz , 50Mhz
output [17:0] LEDR; // red LEDS
output [8:0] LEDG; // green LEDs
output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display
output [6:0] HEX4,HEX5,HEX6,HEX7; //7-segment display
inout [35:0] GPIO;
assign HEX0=7'b111_1111;
assign HEX1=7'b111_1111;
assign HEX2=7'b111_1111;
assign HEX3=7'b111_1111;
assign HEX4=7'b111_1111;
assign HEX5=7'b111_1111;
assign HEX6=7'b111_1111;
assign HEX7=7'b111_1111;

wire oClk_1MHz,oClk100K,oClk10K,oClk1K,oClk100,oClk10,oClk1 ;
MHz50_1MHz u1 (CLOCK_50,KEY[0],oClk_1MHz);
clk_1Hz u2 (oClk_1MHz,KEY[0],oClk100K,oClk10K,oClk1K,oClk100,oClk10,oClk1);
assign LEDR[17] = oClk1;

//module d_flip_flop_edge_triggered(Q, Qn, C, D);
// output Q;
// output Qn;
// input C;
// input D;
d_flip_flop_edge_triggered U0(
LEDR[0],
LEDR[1],
oClk1,
SW[0] );
endmodule
module MHz50_1MHz(Clk_in , Clr , Clk_out); //除50
input Clk_in , Clr; // 一位元輸入
output reg Clk_out;
reg [4:0] cnt=5'b0_0000;
// counter size calculation according to input and output frequencies
parameter sys_clk = 50000000; // 50 MHz system clock
parameter clkout = 1000000; // 1 MHz clock output
parameter max = sys_clk / (2*clkout); // max-counter size

always@(posedge Clk_in or negedge Clr ) begin
if (~Clr)
begin
cnt <= 0;
end
else if (cnt == max-1 )
begin
cnt <= 0;
Clk_out <= ~Clk_out;
end
else
begin
cnt <= cnt + 1'd1;
end
end
endmodule

// Ch10 clk_1Hz.v
// 由 10M Hz 除頻至 1 Hz
module clk_1Hz (Clk1M,Clr,Clk100K,Clk10K,Clk1K,Clk100,Clk10,Clk1);
input Clk1M,Clr; // 一位元輸入
output Clk100K,Clk10K,Clk1K,Clk100,Clk10,Clk1; // 一位元輸出
div10 D2 (Clk1M , Clr, Clk100K);
div10 D3 (Clk100K, Clr, Clk10K );
div10 D4 (Clk10K , Clr, Clk1K );
div10 D5 (Clk1K , Clr, Clk100 );
div10 D6 (Clk100 , Clr, Clk10 );
div10 D7 (Clk10 , Clr, Clk1 );
endmodule
// Ch10 div10.v
// 除頻 /10
module div10 (Clk_i,Clr,Clk_o);
input Clk_i,Clr; // 一位元輸入
output Clk_o; // 一位元輸出
reg Clk_o; // 宣告為暫存器資料
reg [3:0] Q; // 宣告為暫存器資料
// MOD-10 (BCD) 除頻
always@ (posedge Clk_i or negedge Clr)
if (~Clr )
Q = 0;
else if (Q == 9)
Q = 0;
else
Q = Q + 1;
// 形成對稱方波
always@ (Q)
if (Q <= 4)
Clk_o = 0;
else
Clk_o = 1;
endmodule

module d_flip_flop_edge_triggered(Q, Qn, C, D);
output Q;
output Qn;
input C;
input D;
wire Cn; // Control input to the D latch.
wire Cnn; // Control input to the SR latch.
wire DQ; // Output from the D latch, input to the gated SR latch.
wire DQn; // Output from the D latch, input to the gated SR latch.

not(Cn, C);
not(Cnn, Cn);
d_latch dl(DQ, DQn, Cn, D);
sr_latch_gated sr(Q, Qn, Cnn, DQ, DQn);
endmodule // d_flip_flop_edge_triggered
module d_latch(Q, Qn, G, D);
output Q;
output Qn;
input G;
input D;
wire Dn;
wire D1;
wire Dn1;
not(Dn, D);
and(D1, G, D);
and(Dn1, G, Dn);
nor(Qn, D1, Q);
nor(Q, Dn1, Qn);
endmodule // d_latch
module sr_latch_gated(Q, Qn, G, S, R);
output Q;
output Qn;
input G;
input S;
input R;
wire S1;
wire R1;

and(S1, G, S);
and(R1, G, R);
nor(Qn, S1, Q);
nor(Q, R1, Qn);
endmodule // sr_latch_gated

2021年4月3日星期六

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計D Latch為例(UpLoad to FPGA開發平台)

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計D Latch為例 (UpLoad to FPGA開發平台)

module D_Latch(Q, Qn, G, D);
output Q;
output Qn;
input G;
input D;
wire Dn;
wire D1;
wire Dn1;
not(Dn, D);
and(D1, G, D);
and(Dn1, G, Dn);
nor(Qn, D1, Q);
nor(Q, Dn1, Qn);
endmodule

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計D Latch為例

module D_Latch(Q, Qn, G, D);

output Q;
output Qn;
input G;
input D;
wire Dn;
wire D1;
wire Dn1;
not(Dn, D);
and(D1, G, D);
and(Dn1, G, Dn);
nor(Qn, D1, Q);
nor(Q, Dn1, Qn);
endmodule
`timescale 10ns/10ps
module D_Latch_tb;
wire q;
wire qn;
reg g;
reg d;
D_Latch DUT(
.Q(q),
.Qn(qn),
.G(g),
.D(d)
);
initial begin
g=1'b1;d=1'b0;
#500 $stop;
end
always begin
#50 g=g+1'b1;
end
always begin
#100 d=d+1'b1;
end
endmodule

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計4 bit Adder 全加器為例(UpLoad to FPGA開發平台)

module DE2_115 (SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,HEX4 ,HEX5 ,HEX6,HEX7, GPIO );

input [17:0] SW; // toggle switches

input [7:0] KEY; // Push bottom

input CLOCK_50; //Clock 27MHz , 50Mhz

output [17:0] LEDR; // red LEDS

output [8:0] LEDG; // green LEDs

output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display

output [6:0] HEX4,HEX5,HEX6,HEX7; //7-segment display

inout [35:0] GPIO;

assign HEX0=7'b111_1111;

assign HEX1=7'b111_1111;

assign HEX2=7'b111_1111;

assign HEX3=7'b111_1111;

assign HEX4=7'b111_1111;

assign HEX5=7'b111_1111;

assign HEX6=7'b111_1111;

assign HEX7=7'b111_1111;

//(S, C, V, A, B, Op);

//output [3:0] S; // The 4-bit sum/difference.

//output C; // The 1-bit carry/borrow status.

//output V; // The 1-bit overflow status.

//input [3:0] A; // The 4-bit augend/minuend.

//input [3:0] B; // The 4-bit addend/subtrahend.

//input Op; // The operation: 0 => Add, 1=>Subtract.

ripple_carry_adder_subtractor U0(

LEDR[3:0],

LEDR[4],

LEDR[5],

SW[3:0],

SW[7:4],

SW[8]);

endmodule

module ripple_carry_adder_subtractor(S, C, V, A, B, Op);
output [3:0] S; // The 4-bit sum/difference.
output C; // The 1-bit carry/borrow status.
output V; // The 1-bit overflow status.
input [3:0] A; // The 4-bit augend/minuend.
input [3:0] B; // The 4-bit addend/subtrahend.
input Op; // The operation: 0 => Add, 1=>Subtract.

wire C0; // The carry out bit of fa0, the carry in bit of fa1.
wire C1; // The carry out bit of fa1, the carry in bit of fa2.
wire C2; // The carry out bit of fa2, the carry in bit of fa3.
wire C3; // The carry out bit of fa2, used to generate final carry/borrrow.

wire B0; // The xor'd result of B[0] and Op
wire B1; // The xor'd result of B[1] and Op
wire B2; // The xor'd result of B[2] and Op
wire B3; // The xor'd result of B[3] and Op

// Looking at the truth table for xor we see that
// B xor 0 = B, and
// B xor 1 = not(B).
// So, if Op==1 means we are subtracting, then
// adding A and B xor Op alog with setting the first
// carry bit to Op, will give us a result of
// A+B when Op==0, and A+not(B)+1 when Op==1.
// Note that not(B)+1 is the 2's complement of B, so
// this gives us subtraction.
xor(B0, B[0], Op);
xor(B1, B[1], Op);
xor(B2, B[2], Op);
xor(B3, B[3], Op);
xor(C, C3, Op); // Carry = C3 for addition, Carry = not(C3) for subtraction.
xor(V, C3, C2); // If the two most significant carry output bits differ, then we have an overflow.

full_adder fa0(S[0], C0, A[0], B0, Op); // Least significant bit.
full_adder fa1(S[1], C1, A[1], B1, C0);
full_adder fa2(S[2], C2, A[2], B2, C1);
full_adder fa3(S[3], C3, A[3], B3, C2); // Most significant bit.
endmodule // ripple_carry_adder_subtractor

module full_adder(S, Cout, A, B, Cin);
output S;
output Cout;
input A;
input B;
input Cin;

wire w1;
wire w2;
wire w3;
wire w4;

xor(w1, A, B);
xor(S, Cin, w1);
and(w2, A, B);
and(w3, A, Cin);
and(w4, B, Cin);
or(Cout, w2, w3, w4);
endmodule // full_adder

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計4 bit Adder 全加器為例

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計4 bit Adder 全加器 Testbench為例

Compiler??? : Quartus II 9.1sp2 + ModelSim-Altera
Testbench
ripple_carry_adder_subtractor(S, C, V, A, B, Op);
*/
`timescale 10ns/10ps
module add_4_v_tb;
reg [3:0] a;
reg [3:0] b;
reg Op;
wire [3:0] s;
wire co;
wire over;
ripple_carry_adder_subtractor DUT(
.A(a),
.B(b),
.Op(Op),
.S(s),
.C(co),
.V(over)
);
initial begin
a=4'h0;b=4'h0;Op=1'b0;
#1500 Op=1'b1;
#3000 $stop;
end
always begin
#50 a=a+1;
end
always begin
#100 b = a + 1;
end
endmodule
module ripple_carry_adder_subtractor(S, C, V, A, B, Op);
output [3:0] S; // The 4-bit sum/difference.
output C; // The 1-bit carry/borrow status.
output V; // The 1-bit overflow status.
input [3:0] A; // The 4-bit augend/minuend.
input [3:0] B; // The 4-bit addend/subtrahend.
input Op; // The operation: 0 => Add, 1=>Subtract.

wire C0; // The carry out bit of fa0, the carry in bit of fa1.
wire C1; // The carry out bit of fa1, the carry in bit of fa2.
wire C2; // The carry out bit of fa2, the carry in bit of fa3.
wire C3; // The carry out bit of fa2, used to generate final carry/borrrow.

wire B0; // The xor'd result of B[0] and Op
wire B1; // The xor'd result of B[1] and Op
wire B2; // The xor'd result of B[2] and Op
wire B3; // The xor'd result of B[3] and Op
// Looking at the truth table for xor we see that
// B xor 0 = B, and
// B xor 1 = not(B).
// So, if Op==1 means we are subtracting, then
// adding A and B xor Op alog with setting the first
// carry bit to Op, will give us a result of
// A+B when Op==0, and A+not(B)+1 when Op==1.
// Note that not(B)+1 is the 2's complement of B, so
// this gives us subtraction.
xor(B0, B[0], Op);
xor(B1, B[1], Op);
xor(B2, B[2], Op);
xor(B3, B[3], Op);
xor(C, C3, Op); // Carry = C3 for addition, Carry = not(C3) for subtraction.
xor(V, C3, C2); // If the two most significant carry output bits differ, then we have an overflow.

full_adder fa0(S[0], C0, A[0], B0, Op); // Least significant bit.
full_adder fa1(S[1], C1, A[1], B1, C0);
full_adder fa2(S[2], C2, A[2], B2, C1);
full_adder fa3(S[3], C3, A[3], B3, C2); // Most significant bit.
endmodule // ripple_carry_adder_subtractor

module full_adder(S, Cout, A, B, Cin);
output S;
output Cout;
input A;
input B;
input Cin;

wire w1;
wire w2;
wire w3;
wire w4;

xor(w1, A, B);
xor(S, Cin, w1);
and(w2, A, B);
and(w3, A, Cin);
and(w4, B, Cin);
or(Cout, w2, w3, w4);
endmodule // full_adder

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