2020年1月3日 星期五

Master-Slave D Flip-Flop

Master-Slave D Flip-Flop




module MastreSlave_D_FF(d,reset,clk,q,qbar);
 input d,clk,reset;
 output q,qbar;
 Master M1(d,reset,clk,qx,qbarx);
 Master S2(qx,reset,!clk,q,qbar);
endmodule

 module Master(d,reset,clk,q,qbar);
 input d,reset,clk;
 output reg q,qbar;
 initial
  q = 0;
 always @(posedge clk)begin
if(~reset)begin
q <= d;
qbar <= !d;
end
else begin
q <= 1'bz;
qbar <= 1'bz;
end
 end

endmodule


// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps    
module Test_bench;

// Inputs
reg clk=0,d=0,reset=1;

// Outputs
wire q,qba;

// Instantiate the Unit Under Test (UUT)
//module MastreSlave_D_FF(d,reset,clk,q,qbar);
MastreSlave_D_FF UUT(d,reset,clk,q,qba);

   initial begin
    $monitor(clk,d,reset,q,qba);
    // Initialize Inputs
#25 d=1; 
reset=0;
#25 d=0; 
#25 d=1; 
#25 d=1; 
reset=1;
#25 d=0; 
reset=0;
#25 d=1;
#25 d=0; 
#25 d=1; 
#25 d=0;
   end

   always #10 clk<=~clk;
   initial begin
#300;   // 模擬終止時間  300 ns
$stop;
   end
endmodule



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Verilog mod 4 counter using T flip flop

Verilog  mod 4 counter using T flip flop



module mod_16_4bit_counter( sysclk,Q);
   input sysclk;
   output wire [3:0]Q;

    T_FlipFlop       num_1(.clk(sysclk),.T(1'b1),.Q(Q[0]));
    T_FlipFlop       num_2(.clk(Q[0]),.T(1'b1),.Q(Q[1]));
    T_FlipFlop       num_3(.clk(Q[1]),.T(1'b1),.Q(Q[2])); 
    T_FlipFlop       num_4(.clk(Q[2]),.T(1'b1),.Q(Q[3]));

endmodule
       
//======================================       
module T_FlipFlop( clk,T, Q);
   input wire clk;
   input wire T;
   output reg Q;
   wire D;

   initial
   begin
      Q<=1'b0;
   end

   assign  D= T ^ Q;

      always @(negedge clk)
       begin
        Q<=D;
       end
endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps    
module Test_bench;

// Inputs
reg sysclk;

// Outputs
wire [3:0]Q;

// Instantiate the Unit Under Test (UUT)
mod_16_4bit_counter UUT (
    .sysclk(sysclk),
    .Q(Q) 
    );

   initial begin
    $monitor(sysclk,Q);
    // Initialize Inputs
    sysclk <= 1'b1;

      #400 $finish();
   end

    always #10 sysclk=~sysclk;

endmodule
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JK flip flop behavioral verilog

JK flip flop behavioral verilog



//JK 正反器(Flip-Flop)
module JK_FF_behavioral(J,K,CLK,Q,Qn);
       output Q,Qn;
       input J,K,CLK;
  
       reg Q;
       assign Qn = ~ Q ;
  
       always @ (posedge CLK)
       case ({J,K})
              2'b00: Q = Q;
              2'b01: Q = 1'b0;
              2'b10: Q = 1'b1;
              2'b11: Q = ~ Q;
       endcase
endmodule


// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps     
module Test_bench;
   reg   CLK=1;
   reg   J;
   reg   K;   
   wire  Q;
   wire  Qn;   
   
   //module JK_FF_behavioral(J,K,CLK,Q,Qn);
   // Instantiate the Unit Under Test (UUT)
   initial begin
   // Initialize Inputs
       J = 0; K = 0;
       #15 J = 1;K = 1;
       #15 J = 0;K = 1;
       #15 J = 1;K = 0;
       #15 J = 1;K = 1;
       #15 J = 1;K = 0;
       #15 J = 0;K = 1;
       #15 J = 1;K = 1;
       #15 J = 0;K = 1;
    
    end

    JK_FF_behavioral  DUT(J,K,CLK,Q,Qn);
initial begin
#150  $stop;
end
    always #10 CLK=!CLK;

endmodule
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2020年1月2日 星期四

Verilog JK Flip-Flop

Verilog JK Flip-Flop
// JK 型正反器

module JK_FF(input clk, J, K, output Q, Q_not);
    wire    wl0, wl1;

    nand    g0 (wl0, clk, J, Q_not),
            g1 (wl1, clk, K, Q),
            g2 (Q, wl0, Q_not),
            g3 (Q_not, wl1, Q);
endmodule


// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps     
module Test_bench;
   reg   clk;
   reg   J;
   reg   K; 
   wire  Q;
   wire  Q_not; 
   // Instantiate the Unit Under Test (UUT)
   initial begin
   // Initialize Inputs
       J = 0;
       K = 0;
       fork
       #5  J = 0;K = 1;
       #15 J = 1;K = 1;
       #15 J = 1;K = 0;
       #25 J = 1;K = 0;
       #25 J = 1;K = 1;
       #50 J = 0;K = 1;
       #50 J = 0;K = 0;
       #60 J = 0;K = 1;
       clk = 0;
       join
      // Wait 100 ns for global reset to finish
       #70;
     
    end

    JK_FF DUT(clk, J, K, Q, Q_not);
initial begin
#80  $stop;
end
    always #5 clk=!clk;

endmodule



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Verilog modulo-4 up/down counter

Verilog modulo-4 up/down counter



The figure at left is the state diagram for a modulo-4
up-counter.  It just counts 0, 1, 2, 3 and repeats, continually counting up (modulo 4).  There is no input (other than the clock, which we almost never mention) and no output directly associated with the transitions.  For this type of FSM, the output is associated with the states and not with the transitions.

Figure: State Diagram for a Modulo-4 Up-Counter
Many mathematical models of FSM focus on the state diagram.  For most of our work, it is more convenient to work with the state table of the FSM, a tabular representation of the state diagram.  Translation between the state diagram and state table is automatic.  The state table presents the data in terms of present state Q(t) and next state Q(t+1) using the labeling that most naturally fits the problem.  Here are the state tables for the two FSM above.  Note that eh state table contains exactly the same information as the state diagram.

Present State
Next State / Output

X = 0
X = 1
A
A / 0
B / 0
B
A / 0
C / 0
C
D / 0
C / 0
D
A / 0
E / 0
E
A / 0
C / 1
Figure: State Table for 11011 Sequence Detector, Showing Output


Present State
Next State
0
1
1
2
2
3
3
0
Figure: State Table for a Modulo-Four Up-Counter





module mealy_mod_4(out, in, rst, clk);
output out;
input in;
input clk, rst;
reg [1:0]out=2'd0;

parameter s0=2'd0, s1=2'd1, s2=2'd2, s3=2'd3;
always @(posedge clk or negedge rst)
if(rst==0)begin 
out=s0; 
end
else begin
case (out)
s0: 
if(in==0) begin 
out=s1; 
end
else begin 
out=s3; 
end
s1: 
if(in==0) begin
out=s2; 
end
else begin 
out=s0; 
end
s2: 
if(in==0)begin 
out=s3; 
end
else begin 
out=s1; 
end
s3: 
if(in==0) begin 
out=s0; 
end
else begin 
out=s2; 
end
default: out=s0;
endcase
end
endmodule


// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module Test_bench;
reg in=0;
reg rst=1;
reg clk=1;
wire [1:0]out;

//module mealy_mod_4(out, in, rst, clk);
mealy_mod_4 DUT (.out(out) , .in(in) , .rst(rst), .clk(clk) );

initial begin
$monitor( in, rst, clk, out);
 
in=1'b1; 
rst=1; 
clk=1;
 
#60
in = 1'b1; rst = 1; //1
 
#60
in = 1'b1; rst = 1;
 
#60
in = 1'b1; rst = 1;
 
#60
in = 1'b1; rst = 1;
 
#60
in = 1'b1; rst = 1; //5
#60
in = 1'b0; rst = 1;
 
#60
in = 1'b0; rst = 1;
 
#60
in = 1'b0; rst = 1;
 
#60
in = 1'b0; rst = 1;
 
#60
in = 1'b0; rst = 1; //10
#60
in = 1'b0; rst = 1;
#60
in = 1'b0; rst = 1;
 
  #60
in = 1'b1; rst = 1;

  #60
in = 1'b1; rst = 0; //14
 
  #60
in = 1'b0; rst = 0; //15
 
  #60
in = 1'b0; rst = 0; //16
end
always #25 clk <= ~clk;

initial
begin
  #1000;   // 模擬終止時間  1500 ns
    $stop;
end

endmodule  
 

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Mealy Machine Verilog code

Mealy Machine Verilog code





module mealy_1(out, in, rst, clk);
output out;
input in;
input clk, rst;
reg out;
reg[1:0] state;
parameter s0=2'd0, s1=2'd1, s2=2'd2, s3=2'd3;
always @(posedge clk or negedge rst)
if(rst==0)begin 
state=s0; 
out=0; 
end
else begin
case (state)
s0: 
if(in==0) begin 
out=0; 
state=s1; 
end
else begin 
out=0; 
state=s0; 
end
s1: 
if(in==0) begin
out=0; 
state=s1; 
end
else begin 
out=0; 
state=s2; 
end
s2: 
if(in==0)begin 
out=0; 
state=s3; 
end
else begin 
out=0; 
state=s0; 
end
s3: 
if(in==0) begin 
out=0; 
state=s1; 
end
else begin 
out=1; 
state=s2; 
end
default: state=s0;
endcase
end
endmodule



// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module Test_bench;
reg in=0;
reg rst=1;
reg clk=1;
wire out;

//module mealy_1(out, in, rst, clk);
mealy_1 DUT (.out(out) , .in(in) , .rst(rst), .clk(clk) );

initial begin
$monitor( in, rst, clk, out);
 
in=1'b1; 
rst=1; 
clk=1;
 
#60
in = 1'b0; rst = 1; //1
 
#60
in = 1'b1; rst = 1;
 
#60
in = 1'b0; rst = 1;
 
#60
in = 1'b1; rst = 1;
 
#60
in = 1'b0; rst = 1; //5
#60
in = 1'b1; rst = 1;
 
#60
in = 1'b0; rst = 1;
 
#60
in = 1'b1; rst = 1;
 
#60
in = 1'b0; rst = 1;
 
#60
in = 1'b1; rst = 1; //10
#60
in = 1'b0; rst = 1;
#60
in = 1'b1; rst = 1;
 
  #60
in = 1'b0; rst = 1;

  #60
in = 1'b1; rst = 0; //14
 
  #60
in = 1'b0; rst = 0; //15
 
  #60
in = 1'b0; rst = 0; //16
end
always #25 clk <= ~clk;

initial
begin
  #1000;   // 模擬終止時間  1500 ns
    $stop;
end

endmodule  
 
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2020年1月1日 星期三

Verilog J K Flip Flop

Verilog J K Flip Flop 





module JK_FF(input reset, input clk, input j, input k, output reg q, output qnot);
assign qnot=~q;

always @(posedge clk)
  if (reset) q<=1'b0; else
  case ({j, k})
2'b00: q<=q;
2'b01: q<=1'b0;
2'b10: q<=1'b1;
2'b11: q<=~q;
 endcase
endmodule


// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module Test_bench;
reg clk=0;
reg j=0;
reg k=0;
reg reset=1;

wire q, qnot;

  JK_FF DUT(.reset(reset),.clk(clk),.j(j),.k(k),.q(q),.qnot(qnot));

initial begin
$monitor(clk,j,k,q,qnot,reset);
 
j = 1'b0; k = 1'b0;
reset = 1;clk=1;
 
#120
reset=0;j=1'b1; k=1'b0;
 
#120
reset=0;j=1'b0;k=1'b1;
 
#120
reset=0;j=1'b1;k=1'b1;
 
#120
reset=0;j=1'b0;k=1'b0;
 
#120
reset=1;j=1'b1;k=1'b0;
 
end
always #25 clk <= ~clk;

initial
begin
  #580;   // 模擬終止時間  580 ns
    $stop;
end

endmodule  
 
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