輸入 : clock :=48Mhz
reset := push button
輸出：1 digit 7-segment
48Mhz -> 1Hz ->0..9 BCD conuter -> 7segment
----
--VHDL code for BCD to 7-segment display converter
----
--------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cnt_9 is
port (
Clk : in std_logic;
Rst : in std_logic;
segment7 : out std_logic_vector(6 downto 0) -- 7 bit decoded output.
);
end cnt_9;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of cnt_9 is
signal temp: std_logic_vector(0 to 3);
signal Fre_1hz : std_logic ;
--1Hz 基頻
signal Pulse
: std_logic ;
--按鍵防彈跳頻率
begin
Clk_generator: process(Clk)
variable Delay : std_logic_vector(24 downto 0); begin
if rising_edge(Clk) then
if Delay=24000000 then Delay := "0000000000000000000000000" ; --–-將輸入頻率除頻成 1Hz
Fre_1hz <= not Fre_1hz ; else Delay := Delay+1 ; end if ;
Pulse <= Delay(14); ---產生防彈跳頻率
end if ;
end process Clk_generator ;
BCD_CNT: process(Fre_1hz,Rst)
begin
if Rst='1' then
temp <= "0000";
elsif(rising_edge(Fre_1hz)) then
if temp="1001" then
temp<="0000";
else
temp <= temp + 1;
end if;
end if;
end process;
------------------------------------------------------
bcd_7seg: process (clk,temp)
BEGIN
if (Clk'event and Clk='1') then
case temp is
when "0000"=> segment7 <="0000001"; -- '0'
when "0001"=> segment7 <="1001111"; -- '1'
when "0010"=> segment7 <="0010010"; -- '2'
when "0011"=> segment7 <="0000110"; -- '3'
when "0100"=> segment7 <="1001100"; -- '4'
when "0101"=> segment7 <="0100100"; -- '5'
when "0110"=> segment7 <="0100000"; -- '6'
when "0111"=> segment7 <="0001111"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0000100"; -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end if;
end process;
end Behavioral;
