module E_ff(q, data, enable, reset, clock);
output q;
input data, enable, reset, clock;
reg q;
always @(posedge clock) // whenever the clock makes a transition to 1
if (reset == 0)
q = 1'b0;
else if (enable==1)
q = data;
// implicitly : else q = q:
endmodule
module stimulus;
reg data, enable, clock, reset;
wire q;
initial begin
clock = 1'b0;
forever #5 clock = ~clock;
end
E_ff eff0(q, data, enable, reset, clock);
// as with 'c' in the previous section, the wire 'q' will now have its
// value driven into it by the E_ff module.
initial begin
reset = 1'b0;
#10 reset = 1'b1;
data = 1'b1;
#20 enable = 1;
#10 data = 1'b0;
#10 data = 1'b1;
#10 enable = 0;
#10 data = 1'b0;
#10 data = 1'b1;
#10 enable = 1;
#10 reset = 1'b0;
#30 $finish;
end
initial
$monitor($time, " q = %d", q);
endmodule
reg [3:0] output; // output is a 4-bit register
wire [31:0] data; // data is a 32-bit wire
reg [7:0] a;
data[3:0] = output; // partial assignment
output = 4'b0101; // assignment to the whole register
reg [3:0] a; // it is important to adopt one convention for
reg [0:3] b; // the declaration of vector width.
// 1.3 a real number in decimal format
// 1.3e27 a real number in scientific format
real pedantic_pi;
integer relaxed_pi;
initial begin
pedantic_pi = 3.141596259;
relaxed_pi = pedantic_pi; // relaxed_pi is set to 3
end
reg data [7:0]; // 8 1-bit data elements
integer [3:0] out [31:0]; // 32 4-bit output elements
data[5]; // referencing the 5th data element
reg [15:0] mem16_1024 [1023:0]; // memory mem16_1024 is 1K of 16 bit elements
mem16_1024[489]; // referencing element 489 of mem16_1024
module triDriver(bus, drive, value);
inout [3:0] bus;
input drive;
input [3:0] value;
assign #2 bus = (drive == 1) ? value : 4'bz;
endmodule // triDriver
module myTest;
wire [3:0] bus;
reg drive0, drive1, drive2;
integer i;
triDriver mod1 (bus, drive0, i[3:0]);
triDriver mod2 (bus, drive1, 4'hf);
triDriver mod3 (bus, drive2, 4'h0);
initial begin
for (i = 0; i < 12; i = i + 1) begin
#5 {drive2, drive1, drive0} = i;
#5 $display ($time," %b %b %d", i[2:0], bus, bus);
end
$finish;
end // initial begin
endmodule // myTest
10 000 zzzz z
20 001 0001 1
30 010 1111 15
40 011 xx11 X
50 100 0000 0
60 101 0x0x X
70 110 xxxx x
80 111 xxxx x
90 000 zzzz z
100 001 1001 9
110 010 1111 15
120 011 1x11 X
| literals | string (bit & character) numeric real |
| identifiers | module parameter wire register macros (text substitutions) |
| index & slice names | |
| function calls |
| 12'b0011_0101_1100 | - | 12-bit sized binary constant number |
| 2'O57 | - | 2 digit octal number |
| 3_14159 | - | default decimal number |
| 4'h9FDE | - | 4 digit hexadecimal number |
| Verilog Operator | Name | Functional Group |
|---|---|---|
| [ ] | bit-select or part-select | |
| ( ) | parenthesis | |
| ! ~ & | ~& ~| ^ ~^ or ^~ | logical negation negation reduction AND reduction OR reduction NAND reduction NOR reduction XOR reduction XNOR | logical bit-wise reduction reduction reduction reduction reduction reduction |
| + - | unary (sign) plus unary (sign) minus | arithmetic arithmetic |
| { } | concatenation | concatenation |
| {{ }} | replication | replication |
| * / % | multiply divide modulus | arithmetic arithmetic arithmetic |
| + - | binary plus binary minus | arithmetic arithmetic |
| << >> | shift left shift right | shift shift |
| > >= < <= | greater than greater than or equal to less than less than or equal to | relational relational relational relational |
| == != | logical equality logical inequality | equality equality |
| === !== | case equality case inequality | equality equality |
| & | bit-wise AND | bit-wise |
| ^ ^~ or ~^ | bit-wise XOR bit-wise XNOR | bit-wise bit-wise |
| | | bit-wise OR | bit-wise |
| && | logical AND | logical |
| || | logical OR | logical |
| ?: | conditional | conditional |
Node-Red --> MQTT --> Fuxa FUXA（一個開源的 Web HMI / SCADA 自動化監控軟體）的專案設定檔 。 這份設定檔完整定義了 HMI 監控畫面的 後端通訊（MQTT 連線、點位標籤） 與 前端網頁圖形介面（SVG 畫布...
