Digital Electronics (EE101) 2006-2007

Digital Electronics (EE101)   2006-2007

Lecturer: Dr. Conor McArdle

School of Electronic Engineering

Dublin City University

mcardlec@eeng.dcu.ie

Course materials developed by Dr. Derek Molloy and Dr. Ovidiu Ghita

Welcome to the Digital Electronics Course for Engineers

The aim of this course is to provide the student with an introduction

to basic digital electronic devices and their applications. 

Digital circuit design is one of the fundamental areas of 

electronic & mechatronic engineering and computer science.

Laboratory Manual

Laboratory Exercises [Lab 1][Lab 2][Lab 3][Lab 4][Lab 5]

On-line notes

Tutorial Questions

Assignment

Module Description

Past Exam Papers

Syllabus

 

Timetable & Course Structure

Binary Logic: Basic Boolean operators (AND, OR, NOT).

Boolean algebra: De Morgan's Laws. Further Boolean operators (XOR, NAND, NOR). Minimization of logic functions using boolean algebra; using Karnaugh maps, including 3-variable and 4-variable cases.

Binary Arithmetic: Representation of positive integers and fractions in binary notation. Conversion between decimal and binary notations. Addition of binary numbers. Logic circuits for performing binary addition including the half-adder, the full-adder, and the parallel adder.

Binary representation of negative numbers including sign- plus-magnitude, one's complement and two's complement. Addition of negative numbers. Subtraction.

Binary Coded Decimal representation. Addition and subtraction of BCD numbers using the nine's complement method.

Sequential Logic: Sequential logic elements including S-R, D, and J-K flip-flops.

Applications of flip-flops including data registers and shift registers. Asynchronous binary counters. Down counters. Counters with any number of states. Synchronous binary counters. Comparison of maximum frequency of operation of asynchronous and synchronous counters.

2 hours per week for 12 weeks

Monday 10.00 (HG09) and Tuesday 9.00 (CG20)

1 hour per week for 12 weeks

Monday 17.00 (CG28)

One Assignment (10%)Labs: (15%)

 Wednesday 9.00-12.00 (SG16)  (Weeks 2,4,6,8,10)  5 lab sessions  3 hours per week every 2nd week  Must complete pre-lab questions before lab  Lab notebook required  Students' attendance will be recorded by demonstrator

4 questions out of 5 (75%)

Instruction Approach

The course consists of lectures, homework assignments, dedicated tutorial sessions and coursework. The coursework comprises of laboratory based experimentation. Students must complete their coursework successfully before they are eligible to sit the end-of-year exam. For more information see the Module Descriptor.

Recommended Texts

Lectures:

Tutorials:

Coursework:

Exam:

"Digital Fundamentals",

7th Edition,

Merrill  

2000

Restricted Loan (621.3815) 4 copies and 1 in 24 hour loan

3rd edition 2 copies in main lending - 1 lost (621.3815)

2nd edition 1 copy (621.3815)

On-Line Digital Electronics Coursework Manual

DCU

1997

DCU

2003

Use the Internet version.

Additional Texts

T.L. Floyd,
D. Molloy,
O. Ghita & D. Molloy,	On-Line Digital Electronics  Lecture Notes

"Digital Design from Zero to One",

Available in shop - no copies in library as yet.

"Fundamentals of logic design"

Fourth Edition

West

One copy in main lending (621.395)

"Logic Circuits"

Third Edition

McGraw-Hill

3rd ed. One copy in main lending (621.381537)

2nd ed. One copy lost (621.381537)

"Digital Logic and Computer Design"

First Edition 

Prentice-Hall 

4 copies in main lending (621.38195835)

EE101 Digital Electronics - Design and content developed by Derek Molloy. All documents and images ©Derek Molloy 1998-2006. Please do not reproduce anything from these pages without his expressed permission.

Daniels, J.D.,	First Edition	Wiley	1996
Roth, C.H.,	1992
Morris, N.M.,	1983
Mano, M.M.,	1979

Band Pass Filter Calculator

The filter topology here is actually a subset of the MFB topology. However, most programs and calculators for the MFB topology give no consideration of component value sensitivities - hence the need for this calculator. Equations were actually developed empirically from the Deliyannis bandpass topology, which I quickly realized could be converted to the MFB by the addition of a single resistor. By using this "modified Deliyannis" way of calculating the components, a filter can be easily designed that has low sensitivity to component value variations.

Notes:

• The gain and Q of the filter are linked together in this topology - a Q of 10 will also produce a gain of 10, etc.
• Practical limits are a Q of about 50 on the high end, and 1 on the low end.
• For values of Q less than 0.5, consider cascading a high pass filter and a low pass filter - the results will be better than you can get with this calculator
• The open loop gain of the op amp selected must be at least 40 dB greater than the gain of the op amp at the resonant frequency.
• The input impedance of the op amp becomes important as RQ1 increases in value, for large values of Q you may need an FET input type op amp. You can combat this by scaling the R's and C's, but remember you need to use an NPO type capacitor for stability.

Enter Desired Center Frequency (Hz): Enter Desired Q (and Gain V/V): Select Resistor Sequence:            E96           E24         Select Capacitor Sequence:            E24           E12           E6         Select Resistor Scale (Ohms):           1          10          100          1000          10000          100000          1000000        C1, C2 (pF) Ro (Ohms) Rq2 (Ohms) Ro + Rq1 (Ohms)

Digital Labs using the Altera DE2 Board

The Altera DE2 Board, featuring an an Altera Cyclone II^® FPGA, offers varied technology suitable for a wide range of design projects.

Mechanics of DE2 Projects

These projects cover the use of the switches, LEDs, and seven-segment displays on the DE2 board.
The first project discusses the mechanics of Altera DE2 projects, using Quartus and downloading programs to the DE2 board.

Project	Description
diglab1	The user can set a 16-bit value using toggle switches 15-0 and transfer this value to the first four hex digit displays by pressing KEY3.
diglab2	This lab illustrates the use of divide-by-N counters, decimal counters, and a simple hex counter.
diglab3	This lab implements a timer. KEY3 starts and stops the timer. KEY0 resets the count (and stops the timer)

References

• LEDs and switches
• 7-segment displays

LCD Display

Project	Description
lcdlab1	This lab writes two lines to the LCD.
lcdlab2	The project combines a timer (diglab3) with the LCD display (lcdlab1).
lcdlab3	The project controls the LCD, using code adapted from the VHDL code from Hamblen

Reference

DE2 LCD Module

Audio CODEC

Project	Description
audio1	This lab inputs stereo audio from the line-in phone plug, captures it for inspection (using Signal Tap II), and then outputs it to the line-out phone plug.
audio2	Generate signals using a look-up table and output the signal to the line-out phone plug.
audio3	Generate sine waves of specified frequency using direct digital synthesis (DDS)

Reference

DE2 Board Audio CODEC

PS2 Keyboard and Mouse

Project	Description
ps2lab1	This lab reads codes sent from a keyboard attached to the PS2 port.

VGA Controller

Project	Description
vgalab1	This project displays two different test patterns on a VGA display. The choice is made using the SW[0] toggle switch.
vgalab2	Project displays a character table from a 8 pixel wide by 16 pixel high bitmap font.
vgalab3	This project displays a 640 x 480 bitmap (1 bit per pixel) stored in on-chip memory. A MATLAB program is provided to generate the memory initialization file from an image file.

Memory

Project	Description
ramtest	Test the memory access actions of a simple computer.
sramtest	Test the SRAM chip on the DE2 board.

References

• Memory
• DE2 Control Panel

RS232 UART

Project	Description
rs232lab	Send messages in serial form from one DE2 board to another using the RS232 UART.

Reference

• RS232 UART

---

Maintained by John Loomis, last updated 18 November 2009

Altera DE2 Board Resources for Students

Altera DE2 Board Resources for Students
http://users.ece.gatech.edu/~hamblen/DE2/

click DE2 image above to view larger image How to purchase a DE2 board
New DE1 info is here
New Camera and LCD info is here

DE2 Design Examples

DE2 Clock is a clock/timer that uses the DE2's LCD to display the current time. A VHDL-based state machine is used to communicate with the LCD display controller. The Key2 pushbutton resets the time. All VHDL source code is included.Rapid Prototyping of Digital Systems SOPC Edition  now available from Springer Publishing ISBN 978-0-387-72670-0. Source code and documentation can be found in the book and design files are on the DVD.
NOTE: Right click and use Save Target As for the *.sof programming files below:
PS/2 keyboard demo – displays keyboard make and break scan codes in hex on the LCD
PS/2 mouse demo – displays mouse data on the LCD
Moving Ball video display – displays a moving ball on a VGA monitor
MIPS Processor core – runs a short MIPS program on the MIPS processor core from Patterson and Hennessey, Computer Organization and Design on a VGA monitor and the LCD. Pushbuttons reset and single step the processor.
Available in Rapid Prototyping of Digital Systems: A complete NIOS II DE2 hardware and software tutorial – develops a Nios II hardware design and runs a short C program on a NIOS II processor that blinks the LEDs and tests the DE2's  memory and I/O. Uses SOPC Builder and the NIOS II IDE tool to download and run. A uClinux port for the DE2 is also included.

DE2 Hardware Datasheets & Resources

DE2 Hardware Reference Manual
DE2 Schematic
DE2 Chip Datasheets         Additional Data on DE2 I/O Devices
LCD Module - GDM1602A   and LCD controller timing here
3V to 5V conversion   Bus switch IDTQS3384

Bus and Interfacing Resources

I2C Bus Summary
Serial, Parallel, and USB books & links
Software to monitor Serial, USB ports, and Ethernet Traffic on a PC
Interfacing external hardware

DE2 Software Resources

Altera DE2 demos
Altera DE2 labs
Altera DE2 tutorials
Introduction to Quartus
Quartus Reference Manual Vol. 1
Quartus Reference Manual Vol. 2
Quartus Reference Manual Vol. 3
NIOS II Processor Manuals
Ram Megafunction User Guide
Quartus Web Version Software

This web page is not associated with or sponsored by Altera Corporation. Altera is a trademark and service mark of Altera Corporation in the United States and other countries.  Altera products are the intellectual property of Altera Corporation and are protected by copyright laws and one or more U.S. and foreign patents and patent applications.

FPGA系統設計實務(4/6)

FPGA系統設計實務(4/6)

http://www.4shared.com/web/preview/doc/QsQz_bkyba?

FPGA系統設計實務(3/6)

http://www.4shared.com/web/preview/doc/XPklJ2nHce?

修改 2x1 MUX 成為8組 2x1 MUX 並送至2個7段顯示器上顯示結果 並下載到DE2-70 板子

修改 2x1 MUX 成為8組 2x1 MUX
並送至2個7段顯示器上顯示結果

 並下載到DE2-70 板子 

¡Input x  SW[0-7]

¡Input y  SW[8-15]

¡Input SW17 select X or Y

¡Output LEDG0-7

module mux8_2x1disp (SW,LEDR,LEDG,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7);

input [17:0] SW;

output [17:0] LEDR;

output [7:0] LEDG;

output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7;

assign HEX2=7'b111_1111;  //off 7-segment Display

assign HEX3=7'b111_1111; 

assign HEX4=7'b111_1111;

assign HEX5=7'b111_1111;

assign HEX6=7'b111_1111;

assign HEX7=7'b111_1111;

wire [7:0]T1;

 mux8_2x1 c0 (SW[16],SW[7:0],SW[15:8],T1);

 assign LEDR[7:0] = T1;

 hex_7seg c1(T1[3:0],HEX0);

hex_7seg c2(T1[7:4],HEX1);

endmodule

//===============================

module mux8_2x1(sel,a,b,z);

parameter WIDTH=8;

input [WIDTH-1:0] a,b;

output [WIDTH-1:0]z;

input sel;

assign z = sel ? a : b;

endmodule

//===============================

module hex_7seg (hex,seg_out);

  input [3:0] hex;

  output reg [6:0] seg_out;

always@ (hex)

begin

  case (hex)

    //                     gfe_dcba 7-segment

    4'b0000 : seg_out  = 7'b100_0000;

    4'b0001 : seg_out  = 7'b111_1001;

    4'b0010 : seg_out  = 7'b010_0100;

    4'b0011 : seg_out  = 7'b011_0000;

    4'b0100 : seg_out  = 7'b001_1001;

    4'b0101 : seg_out  = 7'b001_0010;

    4'b0110 : seg_out  = 7'b000_0010;

    4'b0111 : seg_out  = 7'b111_1000;

    4'b1000 : seg_out  = 7'b000_0000;

    4'b1001 : seg_out  = 7'b001_0000;

    4'b1010 : seg_out  = 7'b000_1000;

    4'b1011 : seg_out  = 7'b000_0011;

    4'b1100 : seg_out  = 7'b100_0110;

    4'b1101 : seg_out  = 7'b010_0001;

    4'b1110 : seg_out  = 7'b000_0110;

    default : seg_out  = 7'b000_1110;

    endcase

  end

 

endmodule

//===============================

/*

4'b0001 : seg = 8'b11111001;   //1 = F9H
       4'b0010 : seg = 8'b10100100;   //2 = A4H
       4'b0011 : seg = 8'b10110000;   //3 = B0H
       4'b0100 : seg = 8'b10011001;   //4 = 99H
       4'b0101 : seg = 8'b10010010;   //5 = 92H
       4'b0110 : seg = 8'b10000010;   //6 = 82H
       4'b0111 : seg = 8'b11111000;   //7 = F8H
       4'b1000 : seg = 8'b10000000;   //8 = 80H
       4'b1001 : seg = 8'b10010000;   //9 = 90H
       4'b1010 : seg = 8'b10001000;   //A = 88H
       4'b1011 : seg = 8'b10000011;   //b = 83H
       4'b1100 : seg = 8'b11000110;   //C = C6H
       4'b1101 : seg = 8'b10100001;   //d = A1H
       4'b1110 : seg = 8'b10000110;   //E = 86H
       4'b1111 : seg = 8'b10001110;   //F = 8EH
       default : seg = 8'b11000000;   //0 = C0H    */