LAB12 BCD substrator (BCD減法器 10的補數方式)

LAB12 BCD substrator (BCD減法器 10的補數方式)

LAB10 BCD substrator (BCD減法器) 適用於DE2-70
a - b - bor_in  = {bor_out , diff_out}
0-0=0 , 9-0=9 , 0-9=-9

SW[7:4] 被減數  輸入
SW[3:0] 減數 輸入
HEX0 差  輸出
LEDG[0] 借位  輸出

//------------------------------------

//4-bit BCD substrator  10's Complement 

//Filename : BCD_substrator.v

//------------------------------------

module BCD_10s_comp (SW, LEDR, LEDG , CLOCK_27 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3 );

 input  [17:0] SW;    // toggle switches

 input  [7:0] KEY;       // Push bottom

 input  CLOCK_27;     //Clock 27MHz , 50Mhz

 output [17:0]LEDR;    // red  LEDS   

 output [8:0] LEDG;    // green LEDs

    

 output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display

    

  

 //(Diff , Bor_out, Bor_in, A, B);

 //output Diff [3:0] S;  //Difference output

 //output Bor_out;    //Borrow out

 //input Bor_in;       //Borrow in

 //input [3:0] A, B;  //Input data  minuend /  subtrahend  A-B

 // A-B-Bor_in = Diff , Bor_out

   

    wire [3:0] A,B;   //Input data  minuend /  subtrahend  A-B

    wire [3:0] Diff_tmp;  //Difference output

    wire Bor_out;       //Carry out

    wire [7:0] segout0;   //HEX 0

    assign  A=SW[7:4] ;  //minuend A      

    assign  B=SW[3:0] ;  //subtrahend  B

    assign  LEDR[7:0]=SW[7:0];

    assign  LEDR[17]=SW[17];

    

    reg [3:0] A_tmp,B_tmp1;

    wire [3:0] S_tmp,B_tmp;

wire C4;

reg  [3:0] A_mod,B_mod;

    always @ ( A or B  )

begin

if (A<10)

A_tmp = A;   //若是>9 則為9

else

A_tmp =4'b1001;

  

if (B<10)

B_tmp1 = B;  //若是>9 則為9

else

B_tmp1 =4'b1001;

  

end

 

adder4 U0 (.S(B_tmp), 

.Cout(), 

.A(4'b1010) , 

.B(~B_tmp1), 

.Cin(1'b1));

BCD_4bit_FA U1( .S1(S_tmp),

.Cout1(C4),

.Cin1(1'b0), 

.A1(A_tmp), 

.B1(B_tmp));

    assign Bor_out = ~C4;    

    always @ ( A_tmp or B_tmp or C4 or S_tmp )

begin

        case (Bor_out)

1 : begin 

B_mod = ~S_tmp; //Modified code

A_mod = 4'b1010;

end

0:  begin

B_mod = S_tmp;

A_mod = 4'b0000;

end

endcase

end

adder4 U2 ( .S(Diff_tmp),

.Cout(),

.A(A_mod), 

.B(B_mod),

.Cin(Bor_out));

  

   assign LEDG[0]=Bor_out;

   

_7seg UUT0(.hex((Diff_tmp)),

               .seg(segout0));

    

    assign HEX0=segout0[6:0];

    

   

    assign HEX1=7'b111_1111;

assign HEX2=7'b111_1111;

    assign HEX3=7'b111_1111;

    

endmodule

//******************************************************

 module BCD_4bit_FA ( S1, Cout1, Cin1, A1, B1);

 output [3:0] S1; //Sumation output

 output Cout1;    //Carry out

 input Cin1;      //Carry in

 input [3:0] A1, B1;//Input data

 wire [3:0] A_tmp11,B_tmp11,S_tmp11;

 wire C41;

 reg [3:0] B_mod11;

 reg F1;

 //4-bit binary adder

 adder4 BINADD(

            .S(S_tmp11),

            .Cout(C41),

            .Cin(Cin1),

            .A(A1),

            .B(B1)

           );

 //Modify binary code with '0110'

 adder4 MODADD(

            .S(S1),

            .Cout(),

            .Cin(1'b0),

            .A(S_tmp11),

            .B(B_mod11)

           );

 always @ (Cin1 or A1 or B1 or C41 or S_tmp11)

 begin

 //F=C4+S3(S2+S1)

  F1 = (C41 | (S_tmp11[3] & (S_tmp11[2] | S_tmp11[1])));

  B_mod11 = {1'b0, F1, F1, 1'b0}; //Modified code

 end

 assign Cout1 = F1;

 endmodule

//----------------------

//4-bit unsigned adder

//Filename : adder4.v

//----------------------                                                                                                                                                                                                                   

module adder4(S, Cout, A, B, Cin);

 output [3:0] S;   //4-bit sum

 output Cout;    //Carry out

 input [3:0] A, B; //Inputs

 input Cin;    //Carry in

 //Assign the sum of (A+B+Cin) to Cout and Sum

 assign {Cout, S} = A + B + Cin;

endmodule

//-----------------------------------------

//Common-cathod seven segment display

//using case.....endcase statement

//Filename : sevenseg_case.v

//----------------------------------------- 

module _7seg(hex , seg);

    input  [3:0] hex;

    output [7:0] seg;

    reg    [7:0] seg;

    

        

 // segment encoding

 //      0

 //     ---  

 //  5 |   | 1

 //     ---   <- 6

 //  4 |   | 2

 //     ---

 //      3

 always @(hex)

 begin

  case (hex)

       // Dot point is always disable

       4'b0001 : seg = 8'b11111001;   //1 = F9H

       4'b0010 : seg = 8'b10100100;   //2 = A4H

       4'b0011 : seg = 8'b10110000;   //3 = B0H

       4'b0100 : seg = 8'b10011001;   //4 = 99H

       4'b0101 : seg = 8'b10010010;   //5 = 92H

       4'b0110 : seg = 8'b10000010;   //6 = 82H

       4'b0111 : seg = 8'b11111000;   //7 = F8H

       4'b1000 : seg = 8'b10000000;   //8 = 80H

       4'b1001 : seg = 8'b10010000;   //9 = 90H

       4'b1010 : seg = 8'b10001000;   //A = 88H

       4'b1011 : seg = 8'b10000011;   //b = 83H

       4'b1100 : seg = 8'b11000110;   //C = C6H

       4'b1101 : seg = 8'b10100001;   //d = A1H

       4'b1110 : seg = 8'b10000110;   //E = 86H

       4'b1111 : seg = 8'b10001110;   //F = 8EH

       default : seg = 8'b11000000;   //0 = C0H

     endcase

   end

   

endmodule

Programming --> Logic

Programming Logic One and Two Input Gates Three Input Gates Boolean Algebra Theorems Useful Logical Programming Tools Notes Other Resources One and Two Input Gates AND Gate NAND Gate Output is TRUE only if both inputs are TRUE. Output is FALSE only if both inputs are TRUE. A    B output F    F F F    T F T    F F T    T T        A    B output 0    0 0 0    1 0 1    0 0 1    1 1 (The AND gate is useful for masking or clearing specified bit positions.) A    B output F    F T F    T T T    F T T    T F        A    B output 0    0 1 0    1 1 1    0 1 1    1 0 OR Gate NOR Gate Output is TRUE if either input (or both) is TRUE. Output is FALSE if either input (or both) is TRUE. A    B output F    F F F    T T T    F T T    T T        A    B output 0    0 0 0    1 1 1    0 1 1    1 1 (The OR gate is useful for setting specified bits.) A    B output F    F T F    T F T    F F T    T F        A    B output 0    0 1 0    1 0 1    0 0 1    1 0 XOR (EXCLUSIVE OR) Gate XNOR (EXCLUSIVE NOR) Gate (or Equality Gate) Output is TRUE if either input (but not both) is TRUE. Output is FALSE if either input (but not both) is TRUE. A    B output F    F F F    T T T    F T T    T F        A    B output 0    0 0 0    1 1 1    0 1 1    1 0 (The XOR gate is useful for complementing specified bits.) A    B output F    F T F    T F T    F F T    T T        A    B output 0    0 1 0    1 0 1    0 0 1    1 1 NOT Function (or Inverter or Complement Function)     A output F T T F        A output 0 1 1 0 (The NOT function is useful for complementing every bit.)   Three Input Gates AND Gate NAND Gate Output is TRUE only if all inputs are TRUE. Output is FALSE only if all inputs are TRUE. A    B    C output F    F    F F F    F    T F F    T    F F F    T    T F T    F    F F T    F    T F T    T    F F T    T    T T        A    B    C output 0    0    0 0 0    0    1 0 0    1    0 0 0    1    1 0 1    0    0 0 1    0    1 0 1    1    0 0 1    1    1 1 A    B    C output F    F    F T F    F    T T F    T    F T F    T    T T T    F    F T T    F    T T T    T    F T T    T    T F        A    B    C output 0    0    0 1 0    0    1 1 0    1    0 1 0    1    1 1 1    0    0 1 1    0    1 1 1    1    0 1 1    1    1 0 OR Gate NOR Gate Output is TRUE if any input (or all) is TRUE. Output is FALSE if any input (or all) is TRUE. A    B    C output F    F    F F F    F    T T F    T    F T F    T    T T T    F    F T T    F    T T T    T    F T T    T    T T        A    B    C output 0    0    0 0 0    0    1 1 0    1    0 1 0    1    1 1 1    0    0 1 1    0    1 1 1    1    0 1 1    1    1 1 A    B    C output F    F    F T F    F    T F F    T    F F F    T    T F T    F    F F T    F    T F T    T    F F T    T    T F        A    B    C output 0    0    0 1 0    0    1 0 0    1    0 0 0    1    1 0 1    0    0 0 1    0    1 0 1    1    0 0 1    1    1 0 XOR (EXCLUSIVE OR) Gate XNOR (EXCLUSIVE NOR) Gate A    B    C output F    F    F F F    F    T T F    T    F T F    T    T F T    F    F T T    F    T F T    T    F F T    T    T T        A    B    C output 0    0    0 0 0    0    1 1 0    1    0 1 0    1    1 0 1    0    0 1 1    0    1 0 1    1    0 0 1    1    1 1 A    B    C output F    F    F T F    F    T F F    T    F F F    T    T T T    F    F F T    F    T T T    T    F T T    T    T F        A    B    C output 0    0    0 1 0    0    1 0 0    1    0 0 0    1    1 1 1    0    0 0 1    0    1 1 1    1    0 1 1    1    1 0 Boolean Algebra Theorems AND theorems 0 · 0 = 0 A · 1 = A 1 · 1 = 1 A · A = A 1 · 0 = 0 A · /A = 0 A · 0 = 0   OR theorems 1 + 1 = 1 A + 0 = A 0 + 0 = 0 A + A = A 1 + 0 = 1 A + /A = 1 A + 1 = 1   NOT /0 = 1 /1 = 0 //A = A   Commutation A + B = B + A A · B = B · A Absorption A + A · B = A A · (A + B) = A Association A + (B + C) = (A + B) + C A · (B · C) = (A · B) · C Distribution A + B · C = (A + B) · (A + C) A · (B + C) = A · B + A · C DeMorgan's theorems /A + /B = /A · /B /A · /B = /A + /B Useful Logical Programming Tools IF N AND 1 THEN Tests if a number is odd (has its bit 1 set) N + N AND -2 Always gives the even number of a pair, so if you are calculating an offset into a buffer, this always places you at an even-numbered position. N = N AND X Keeps a variable within a range X. So N AND 16383 insures that an integer never exceeds 16383. N = N AND 127 Clears the high bit (bit 8) in characters such as for sending to a serial port. N = N OR 128 Sets the high bit (bit 8) in characters. In some cases this signals an attribute such as underlining. N = N AND 95 Changes an lower case ASCII letter character to upper case by clearing bit 6. Replaces IF (ASCII CODE N) > 96 THEN N = N - 32. N = N OR 32 Changes an upper case ASCII letter character to lower case by setting bit 6. N = N AND 15 Converts an ASCII number character into its decimal number value by clearing bits 5 and 6. N = N OR 48 Converts the digits 0 to 9 into their printable ASCII codes by setting bits 5 and 6. IF X OR Y If either X or Y has a nonzero value ... X = X XOR 1 Sets a flag variable from 1 or -1 to 0 and back. Replaces IF X THEN X = 0 ELSE X = 1. PAGE = PAGE XOR 3 XOR can be used jump back and forth between two values, here between video pages 1 and 2. The value that toggles between has 1's where changes occur and 0 where they don't, for example to switch between   3  00000011 and 45  00101101 use 46  00101110 X = X + 1 AND 3 This can be used to maintain a cycle. Replaces X = X + 1: IF X = 4 THEN X = 0. X = 1 - X Toggles a variable between 1 and 0. Notes FALSE = F = 0 TRUE = T = 1   Positive Logic (or Positive True Logic or High True Logic) FALSE or 0 = LOW TRUE or 1 = HIGH   Negative Logic (or Negative True Logic or Low True Logic) FALSE or 0 = HIGH TRUE or 1 = LOW   Bit_Logic.vi:  A LabVIEW program that demonstrates bit-wise logic operations. Other Resources Binary Arithmetic Digital Logic Gates [  Index  |  Technical Notes  ] DISCLAIMER Page author: Dawn Rorvik (rorvikd@evergreen.edu) Last modified: 11/17/2006

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http://academic.evergreen.edu/projects/biophysics/technotes/

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設計一個3位的BCD 下數計數器,計數範圍999~000。

//設計一個3位的BCD 下數計數器。其值按秒遞減，輸出顯示在HEX2~0上，用KEY0復位。計數器的控制信號由50MHz的時鐘提供。
//分析：
//1. 按秒遞減計數，所以要把50MHz的時鐘分頻得到1Hz的脈衝。
//2. 3位元BCD計數器，可用1位元BCD計數器組合，其計數範圍999~000。
//Part I 代碼如下：
// 50_000_000(10)=2FAF080(16)    2+24=26bit

 module BCD_999_000 (CLOCK_50,KEY,HEX2,HEX1,HEX0);
 output [6:0]HEX2,HEX1,HEX0; //輸出顯示
 input CLOCK_50; //50MHz時鐘
 input [0:0]KEY; //復位

 wire clk_1hz; //1hz時鐘信號 
 wire [11:0]cnt; //計數器輸出
 wire e2,e3;
 supply1 vdd;

 assign e2=~cnt[3]&~cnt[2]&~cnt[1]&~cnt[0];   
   //0000-> enable 上一位 -1
 assign e3=e2&(~cnt[7]&~cnt[6]&~cnt[5]&~cnt[4]);   
 //0000-> enable 上一位 -1

 //分頻產生1hz的脈衝
 _1HZ u0 (.CLK(CLOCK_50),
 .RSTn(KEY), 
 .HZ_1(clk_1hz));

 //3-digit BCD計數器
 counter10 u1(.en(vdd),
 .clk(clk_1hz),
 .rst_n(KEY),
 .q(cnt[3:0])
);

 counter10 u2(.en(e2),
 .clk(clk_1hz),
 .rst_n(KEY),
 .q(cnt[7:4])
  );
  
 counter10 u3(.en(e3),
 .clk(clk_1hz),
 .rst_n(KEY),
 .q(cnt[11:8])
  );

 //解碼顯示
 _7seg h0 (.hex(cnt[3:0]),.seg(HEX0));
 _7seg h1 (.hex(cnt[7:4]),.seg(HEX1)); 
 _7seg h2 (.hex(cnt[11:8]),.seg(HEX2)); 

 endmodule




//============================================
//BCD counter counts 0 to 9 and then rolls over
//============================================
 module counter10(en,clk,rst_n,q);
output reg [3:0]q;
input en,clk,rst_n;

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
q<=4'b0;
else if(!en)
q<=q;
else if(q==4'b0000)
q<=4'b1001;
else
q<=q-1'b1;
end
 endmodule






module _1HZ (CLK, RSTn, HZ_1);

    input CLK;
    input RSTn;
    output HZ_1;
    
    /*************************************/
    
    parameter T1S = 26'd50_000_000;  //50MHZ 
    
    /*************************************/
    
    reg [25:0]Count1;
    
    always @ ( posedge CLK or negedge RSTn )
    begin
     if( !RSTn ) 
         Count1 <= 26'd0;
     else if( Count1 == T1S )
         Count1 <= 26'd0;
     else
         Count1 <= Count1 + 1'b1;
end        
 /*************************************/

reg rLED_Out;


always @ ( posedge CLK or negedge RSTn )
    begin
        if( !RSTn ) 
            rLED_Out <= 1'b0;
        else if( Count1 >= 26'd0 && Count1 < 26'd25_000_000 )
          //0.5sec ON , o.5sec OFF
            rLED_Out <= 1'b1;
        else 
            rLED_Out <= 1'b0;
     end  
          
     /***************************************/
     
     assign HZ_1 = rLED_Out;
     
     /***************************************/
              
    
endmodule

//-----------------------------------------

//Common-cathod seven segment display

//using case.....endcase statement

//Filename : sevenseg_case.v

//----------------------------------------- 

module _7seg(hex , seg);

    input  [3:0] hex;

    output [7:0] seg;

    reg    [7:0] seg;

    

        

  // segment encoding

 //      0

 //     ---  

 //  5 |   | 1

 //     ---   <- 6

 //  4 |   | 2

 //     ---

 //      3

 always @(hex)

 begin

  case (hex)

       // Dot point is always disable

       4'b0001 : seg = 8'b11111001;   //1 = F9H

       4'b0010 : seg = 8'b10100100;   //2 = A4H

       4'b0011 : seg = 8'b10110000;   //3 = B0H

       4'b0100 : seg = 8'b10011001;   //4 = 99H

       4'b0101 : seg = 8'b10010010;   //5 = 92H

       4'b0110 : seg = 8'b10000010;   //6 = 82H

       4'b0111 : seg = 8'b11111000;   //7 = F8H

       4'b1000 : seg = 8'b10000000;   //8 = 80H

       4'b1001 : seg = 8'b10010000;   //9 = 90H

       4'b1010 : seg = 8'b10001000;   //A = 88H

       4'b1011 : seg = 8'b10000011;   //b = 83H

       4'b1100 : seg = 8'b11000110;   //C = C6H

       4'b1101 : seg = 8'b10100001;   //d = A1H

       4'b1110 : seg = 8'b10000110;   //E = 86H

       4'b1111 : seg = 8'b10001110;   //F = 8EH

       default : seg = 8'b11000000;   //0 = C0H

     endcase

   end

   

endmodule

設計一個3位的BCD上數計數器,計數範圍000~999。

//設計一個3位的BCD計數器。其值按秒遞增，
//輸出顯示在HEX2~0上，用KEY0 RESET
//計數器的控制信號由50MHz的時鐘提供。
//分析：

//1. 按秒遞增計數，所以要把50MHz的時鐘分頻得到1Hz的脈衝。
//2. 3位元BCD計數器，可用1位元BCD計數器組合，其計數範圍000~999。
//Part I 代碼如下：

 module BCD_000_999 (CLOCK_50,KEY,HEX2,HEX1,HEX0);
 output [6:0]HEX2,HEX1,HEX0; //輸出顯示
 input CLOCK_50; //50MHz時鐘
 input [0:0]KEY; //復位

 wire clk_1hz; //1hz時鐘信號 
 wire [11:0]cnt; //計數器輸出
 wire e2,e3;
 supply1 vdd;

 assign e2=cnt[3]&cnt[0];
 assign e3=e2&(cnt[7]&cnt[4]);

 //分頻產生1hz的脈衝
 _1HZ u0 (.CLK(CLOCK_50),
 .RSTn(KEY), 
 .HZ_1(clk_1hz));

 //3-digit BCD計數器
 counter10 u1(.en(vdd),
 .clk(clk_1hz),
 .rst_n(KEY),
 .q(cnt[3:0])
);

 counter10 u2(.en(e2),
 .clk(clk_1hz),
 .rst_n(KEY),
 .q(cnt[7:4])
  );
  
 counter10 u3(.en(e3),
 .clk(clk_1hz),
 .rst_n(KEY),
 .q(cnt[11:8])
  );

 //解碼顯示
 _7seg h0 (.hex(cnt[3:0]),.seg(HEX0));
 _7seg h1 (.hex(cnt[7:4]),.seg(HEX1)); 
 _7seg h2 (.hex(cnt[11:8]),.seg(HEX2)); 

 endmodule

// 50MHZ 變成1HZ

//******************************

module _1HZ (CLK, RSTn, HZ_1);

    input CLK;
    input RSTn;
    output HZ_1;
    
    /*************************************/
    parameter T1S = 26'd50_000_000;  //50MHZ 
    /*************************************/
   //50_000_000(10)=2FAF080(16)    2+24=26bit

    reg [25:0]Count1;
    
    always @ ( posedge CLK or negedge RSTn )
    begin
     if( !RSTn ) 
         Count1 <= 26'd0;
     else if( Count1 == T1S )
         Count1 <= 26'd0;
     else
         Count1 <= Count1 + 1'b1;
end        
 /*************************************/

reg rLED_Out;


always @ ( posedge CLK or negedge RSTn )
    begin
        if( !RSTn ) 
            rLED_Out <= 1'b0;
        else if( Count1 >= 26'd0 && Count1 < 26'd25_000_000 )
          //0.5sec ON , o.5sec OFF
            rLED_Out <= 1'b1;
        else 
            rLED_Out <= 1'b0;
     end  
          
     /***************************************/
     
     assign HZ_1 = rLED_Out;
     
     /***************************************/
              
    
endmodule

//除10 verilog 程式

//******************************

 module counter10(en,clk,rst_n,q);

output reg [3:0]q;

input en,clk,rst_n;

always@(posedge clk or negedge rst_n)

begin

if(!rst_n)

q<=4'b0;

else if(!en)

q<=q;

else if(q==4'b1001)

q<=4'b0;

else

q<=q+1'b1;

end

 endmodule

//-----------------------------------------

//Common-cathod seven segment display

//using case.....endcase statement

//Filename : sevenseg_case.v

//----------------------------------------- 

module _7seg(hex , seg);

    input  [3:0] hex;

    output [7:0] seg;

    reg    [7:0] seg;

    

        

//Binary 轉7-segment  verilog 程式

//******************************

 // segment encoding

 //      0

 //     ---  

 //  5 |   | 1

 //     ---   <- 6

 //  4 |   | 2

 //     ---

 //      3

 always @(hex)

 begin

  case (hex)

       // Dot point is always disable

       4'b0001 : seg = 8'b11111001;   //1 = F9H

       4'b0010 : seg = 8'b10100100;   //2 = A4H

       4'b0011 : seg = 8'b10110000;   //3 = B0H

       4'b0100 : seg = 8'b10011001;   //4 = 99H

       4'b0101 : seg = 8'b10010010;   //5 = 92H

       4'b0110 : seg = 8'b10000010;   //6 = 82H

       4'b0111 : seg = 8'b11111000;   //7 = F8H

       4'b1000 : seg = 8'b10000000;   //8 = 80H

       4'b1001 : seg = 8'b10010000;   //9 = 90H

       4'b1010 : seg = 8'b10001000;   //A = 88H

       4'b1011 : seg = 8'b10000011;   //b = 83H

       4'b1100 : seg = 8'b11000110;   //C = C6H

       4'b1101 : seg = 8'b10100001;   //d = A1H

       4'b1110 : seg = 8'b10000110;   //E = 86H

       4'b1111 : seg = 8'b10001110;   //F = 8EH

       default : seg = 8'b11000000;   //0 = C0H

     endcase

   end

   

endmodule