LAB11 BCD substrator (BCD減法器)
LAB10 BCD substrator (BCD減法器) 適用於DE2-70
a - b - bor_in = {bor_out , diff_10out, diff_out}
a = SW[15:8] 被減數 輸入 00-99
b= SW[7:0] 減數 輸入 00-99
HEX1-HEX0 差 BCD 輸出
a - b - bor_in = {bor_out , diff_10out, diff_out}
a = SW[15:8] 被減數 輸入 00-99
b= SW[7:0] 減數 輸入 00-99
HEX1-HEX0 差 BCD 輸出
LEDG[0:7]=差 BCD 輸出
LEDG[8] 借位 輸出 (正負號)
//------------------------------------
//8-bit BCD substrator A-B-Bor_in = { Bor_out , Diff_10s_out , Diff_1s_out }
//Filename : BCD_substrator.v
//------------------------------------
module BCD_sub_99(SW, LEDR, LEDG , CLOCK_27 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3 );
input [17:0] SW; // toggle switches
input [7:0] KEY; // Push bottom
input CLOCK_27; //Clock 27MHz , 50Mhz
output [17:0] LEDR; // red LEDS
output [8:0] LEDG; // green LEDs
output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display
wire [3:0] A0,B0; //Input data minuend / subtrahend A-B
wire [7:4] A1,B1; //Input data minuend / subtrahend A-B
reg [3:0] Diff_1s_out; //Difference output
reg [3:0] Diff_10s_out;
reg [3:0] Diff_1s_tmp; //Difference output
reg [3:0] Diff_10s_tmp;
reg [7:0] Diff_Xout;
reg Diff_100s_out;
wire Bor_out; //Borrow out
wire [7:0] segout0; //HEX 0
wire [7:0] segout1; //HEX 1
assign A1=SW[15:12] ; //minuend A
assign A0=SW[11:8] ; //minuend A
assign B1=SW[7:4] ; //subtrahend B
assign B0=SW[3:0] ; //subtrahend B
assign LEDR[15:0]=SW[15:0];
assign LEDR[17]=SW[17];
reg [3:0] A0_tmp,A1_tmp,B0_tmp1,B1_tmp1;
wire [3:0] S0_tmp,S1_tmp,B0_tmp,B1_tmp;
wire C4;
wire C8;
always @ ( A0 or B0 or A1 or B1 )
begin
if (A0<10)
A0_tmp = A0; //若是>9 則為9
else
A0_tmp = 4'b1001;
if (B0<10)
B0_tmp1 = B0; //若是>9 則為9
else
B0_tmp1 =4'b1001;
//******************************
if (A1<10)
A1_tmp = A1; //若是>9 則為9
else
A1_tmp = 4'b1001;
if (B1<10)
B1_tmp1 = B1; //若是>9 則為9
else
B1_tmp1 =4'b1001;
end
_10s_complement U1 (.Xin0(B0_tmp1),
.Xin1(B1_tmp1),
.Xout0(B0_tmp),
.Xout1(B1_tmp)); //10's Complement
BCD_4bit_FA U3 (.S1(S0_tmp),
.Cout1(C4),
.Cin1(1'b0),
.A1(A0_tmp),
.B1(B0_tmp)
);
BCD_4bit_FA U4 (.S1(S1_tmp),
.Cout1(C8),
.Cin1(C4),
.A1(A1_tmp),
.B1(B1_tmp)
);
assign Bor_out=~C8; //Bor_out=1 Negative 0=Positive
always @ (*)
// A0_tmp or B0_tmp or A1_tmp or B1_tmp or C4 or C8 or
// S0_tmp or S1_tmp or Bor_in)
begin
case (Bor_out)
0 : begin
Diff_1s_out = S0_tmp;
Diff_10s_out = S1_tmp;
end
1: begin
Diff_1s_tmp = (~S0_tmp)+4'b1010; //9's Complement
Diff_10s_tmp = (~S1_tmp)+4'b1010;
Diff_Xout = ((Diff_10s_tmp<<4) + Diff_1s_tmp + 4'b1) ; //10's complement
Diff_10s_out = Diff_Xout[7:4];
Diff_1s_out = Diff_Xout[3:0];
end
endcase
end
assign LEDG[8]=Bor_out;
assign LEDG[7:4]=Diff_10s_tmp;
assign LEDG[3:0]=Diff_1s_tmp;
_7seg UUT10(.hex(Diff_1s_out),
.seg(segout0));
assign HEX0=segout0[6:0];
_7seg UUT11(.hex(Diff_10s_out),
.seg(segout1));
assign HEX1=segout1[6:0];
assign HEX2=7'b111_1111;
assign HEX3=7'b111_1111;
endmodule
//----------------------
//4-bit unsigned adder
//Filename : adder4.v
//----------------------
module adder4(S, Cout, A, B, Cin);
output [3:0] S; //4-bit sum
output Cout; //Carry out
input [3:0] A, B; //Inputs
input Cin; //Carry in
//Assign the sum of (A+B+Cin) to Cout and Sum
assign {Cout, S} = A + B + Cin;
endmodule
//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//-----------------------------------------
module _7seg(hex , seg);
input [3:0] hex;
output [7:0] seg;
reg [7:0] seg;
// segment encoding
// 0
// ---
// 5 | | 1
// --- <- 6
// 4 | | 2
// ---
// 3
always @(hex)
begin
case (hex)
// Dot point is always disable
4'b0001 : seg = 8'b11111001; //1 = F9H
4'b0010 : seg = 8'b10100100; //2 = A4H
4'b0011 : seg = 8'b10110000; //3 = B0H
4'b0100 : seg = 8'b10011001; //4 = 99H
4'b0101 : seg = 8'b10010010; //5 = 92H
4'b0110 : seg = 8'b10000010; //6 = 82H
4'b0111 : seg = 8'b11111000; //7 = F8H
4'b1000 : seg = 8'b10000000; //8 = 80H
4'b1001 : seg = 8'b10010000; //9 = 90H
4'b1010 : seg = 8'b10001000; //A = 88H
4'b1011 : seg = 8'b10000011; //b = 83H
4'b1100 : seg = 8'b11000110; //C = C6H
4'b1101 : seg = 8'b10100001; //d = A1H
4'b1110 : seg = 8'b10000110; //E = 86H
4'b1111 : seg = 8'b10001110; //F = 8EH
default : seg = 8'b11000000; //0 = C0H
endcase
end
endmodule
//----------------------
//Filename : nine's complement
//----------------------
module _10s_complement(Xin1 , Xin0 , Xout1 , Xout0 );
output [3:0] Xout1; //4-bit 10's complement
output [3:0] Xout0; //4-bit 10's complement
input [3:0] Xin1; //Inputs
input [3:0] Xin0; //Inputs
wire [7:0] Xout;
wire [3:0] Xout0_tmp;
wire [3:0] Xout1_tmp;
//Assign the 9's complement Xout = ~Xin + 1010 ;
assign Xout0_tmp = ~Xin0 + 4'b1010 ;
assign Xout1_tmp = ~Xin1 + 4'b1010 ;
assign Xout = (Xout1_tmp<<4) + Xout0_tmp +4'b1 ;
assign Xout1 = Xout[7:4];
assign Xout0 = Xout[3:0];
endmodule
module BCD_4bit_FA ( S1, Cout1, Cin1, A1, B1);
output [3:0] S1; //Sumation output
output Cout1; //Carry out
input Cin1; //Carry in
input [3:0] A1, B1;//Input data
wire [3:0] A_tmp11,B_tmp11,S_tmp11;
wire C41;
reg [3:0] B_mod11;
reg F1;
//4-bit binary adder
adder4 BINADD(
.S(S_tmp11),
.Cout(C41),
.Cin(Cin1),
.A(A1),
.B(B1)
);
//Modify binary code with '0110'
adder4 MODADD(
.S(S1),
.Cout(),
.Cin(1'b0),
.A(S_tmp11),
.B(B_mod11)
);
always @ (Cin1 or A1 or B1 or C41 or S_tmp11)
begin
//F=C4+S3(S2+S1)
F1 = (C41 | (S_tmp11[3] & (S_tmp11[2] | S_tmp11[1])));
B_mod11 = {1'b0, F1, F1, 1'b0}; //Modified code
end
assign Cout1 = F1;
endmodule
