以Verilog 設計一個數位電路 (EX1_9)--- always --4 bit 4x1 mux 電路

以Verilog 設計一個數位電路 (EX1_9)--- always --4 bit 4x1 mux 電路

 module ex9_4bit_4x1MUX( a,b,c,d, sel,out);  
          
input [3:0] a,b,c,d; // 4-bit input called a ,b,c,d 
input [1:0] sel;    //input sel used to select between a,b,c,d
output reg [3:0] out;   // 4-bit output based on input sel


   // This always block gets executed whenever a/b/c/d/sel changes value
   // When that happens, based on value in sel, output is assigned to either a/b/c/d
   always @ (a or b or c or d or sel) begin
      case (sel)
         2'b00 : out <= a;
         2'b01 : out <= b;
         2'b10 : out <= c;
         2'b11 : out <= d;
      endcase
   end

endmodule

`timescale 100 ns/1 ns

module testbench;

/*

module Four_bit_4x1MUX( a,b,c,d, sel,out);            

input [3:0] a,b,c,d; // 4-bit input called a ,b,c,d 

input [1:0] sel     //input sel used to select between a,b,c,d

output [3:0] out;   // 4-bit output based on input sel

*/

reg [3:0] a,b,c,d;

reg [1:0] sel;

wire [3:0] out;

ex9_4bit_4x1MUX UUT( a,b,c,d, sel,out);            

initial begin

a=4'h8;  b=4'h9;  c=4'ha ; d=4'hb;

sel=2'b00;

#20;

sel=2'b01;

#20;

sel=2'b10;

#20;

sel=2'b11;

#20 ;

$stop;

end

endmodule