Verilog code for XNOR gate – All modeling styles

Verilog code for XNOR gate – All modeling styles

Logic Circuit of the XNOR gate

Gate Level modeling

module XNOR_2(output Y, input A, B);
  xnor(Y, A, B);
endmodule

Data flow modeling

Equation of the XNOR gate

The boolean equation of an XNOR gate is Y = AB + A’B’.

module XNOR_2_data_flow (output Y, input A, B);
   assign Y = ~(A ^ B);
endmodule

Behavioral Modeling

Truth Table for XNOR gate

A	B	Y(A XNOR B)
0	0	1
0	1	0
1	0	0
1	1	1

Equation from the truth table

Y = A.B + A’B’ or say Y = A XNOR B.

module XNOR_2_behavioral (output reg Y, input A, B);
always @ (A or B) begin
   if (A == 1'b0 & B == 1'b0) begin
       Y = 1'b1;
   end
   if (A == 1'b1 & B == 1'b1) begin
       Y = 1'b1;
   end
   else 
       Y = 1'b0;
end
endmodule

RTL schematic of XNOR gate

Testbench of the XNOR gate using Verilog

`include "XNOR_2_behavioral.v"

`timescale 100ns/1ns
module XNOR_2_behavioral_tb;
reg A, B;wire Y;
XNOR_2_behavioral Instance0 (Y, A, B);
initial begin
    A = 0; B = 0;
 #10 A = 0; B = 1;
 #10 A = 1; B = 0;
 #10 A = 1; B = 1;

#10 $stop;
   end
initial begin
    $monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y);
    $dumpfile("dump.vcd");
    $dumpvars();
end
endmodule