Verilog SR Latch using Behavior Modeling

Verilog SR Latch using Behavior Modeling 

//=================================================
//Design of SR Latch using Behavior Modeling Style
//=================================================
module RS_Latch( s ,r ,enable ,q ,qb );

output q ;
reg q ;
output qb ;
reg qb ;

input s ;
wire s ;
input r ;
wire r ;
input enable ;
wire enable ;

always @ (enable or s or r ) begin
 if (enable) begin
if (s!=r) begin
q = s; qb = r;
end 
else if (s==1 && r==1) begin
q = 1'bZ; qb = 1'bZ;
end
end
 else
  begin
q = 1'bZ; qb = 1'bZ;
end
end

endmodule


// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps     
module Test_bench;
//module RS_Latch( s ,r ,enable ,reset ,q ,qb );
 reg s,r,enable;
 wire q, qb;

RS_Latch UUT( s ,r ,enable ,q ,qb );

initial begin
    // Initialize Inputs
    s = 0; r = 1;enable=1;
     
    // Add stimulus here
    
    #100 s = 1;r = 0; 
    #100 s = 1;r = 1;
    #100 s = 1;r = 0;
    #100 s = 0;r = 0;
    #100 s = 0;r = 1;
    #100 s = 1;r = 1;
    #100 s = 0;r = 0;
    #100 $stop;
end

endmodule