Mealy Machine Verilog code

Mealy Machine Verilog code

https://www.rfwireless-world.com/source-code/VERILOG/Mealy-Machine-and-Moore-Machine-verilog-code.html

module mealy_1(out, in, rst, clk);

output out;

input in;

input clk, rst;

reg out;

reg[1:0] state;

parameter s0=2'd0, s1=2'd1, s2=2'd2, s3=2'd3;

always @(posedge clk or negedge rst)

if(rst==0)begin 

state=s0; 

out=0; 

end

else begin

case (state)

s0: 

if(in==0) begin 

out=0; 

state=s1; 

end

else begin 

out=0; 

state=s0; 

end

s1: 

if(in==0) begin

out=0; 

state=s1; 

end

else begin 

out=0; 

state=s2; 

end

s2: 

if(in==0)begin 

out=0; 

state=s3; 

end

else begin 

out=0; 

state=s0; 

end

s3: 

if(in==0) begin 

out=0; 

state=s1; 

end

else begin 

out=1; 

state=s2; 

end

default: state=s0;

endcase

end

endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps

module Test_bench;

reg in=0;

reg rst=1;

reg clk=1;

wire out;

//module mealy_1(out, in, rst, clk);

mealy_1 DUT (.out(out) , .in(in) , .rst(rst), .clk(clk) );

initial begin

$monitor( in, rst, clk, out);

 

in=1'b1; 

rst=1; 

clk=1;

 

#60

in = 1'b0; rst = 1; //1

 

#60

in = 1'b1; rst = 1;

 

#60

in = 1'b0; rst = 1;

 

#60

in = 1'b1; rst = 1;

 

#60

in = 1'b0; rst = 1; //5

#60

in = 1'b1; rst = 1;

 

#60

in = 1'b0; rst = 1;

 

#60

in = 1'b1; rst = 1;

 

#60

in = 1'b0; rst = 1;

 

#60

in = 1'b1; rst = 1; //10

#60

in = 1'b0; rst = 1;

#60

in = 1'b1; rst = 1;

 

  #60

in = 1'b0; rst = 1;

  #60

in = 1'b1; rst = 0; //14

 

  #60

in = 1'b0; rst = 0; //15

 

  #60

in = 1'b0; rst = 0; //16

end

always #25 clk <= ~clk;

initial

begin

  #1000;   // 模擬終止時間  1500 ns

    $stop;

end

endmodule