Verilog 4Bits Adder gate level

Verilog 4Bits Adder gate level

源自於 http://ccckmit.wikidot.com/ve:adder4

module fulladder (input a, b, c_in, output sum, c_out);
wire s1, c1, c2;

xor g1(s1, a, b);
xor g2(sum, s1, c_in);
and g3(c1, a,b);
and g4(c2, s1, c_in) ;
xor g5(c_out, c2, c1) ;

endmodule

module Adder_4bit(input signed [3:0] a, input signed [3:0] b, input c_in, output signed [3:0] sum, output c_out);
wire [3:0] c;

fulladder fa1(a[0],b[0], c_in, sum[0], c[1]) ;
fulladder fa2(a[1],b[1], c[1], sum[1], c[2]) ;
fulladder fa3(a[2],b[2], c[2], sum[2], c[3]) ;
fulladder fa4(a[3],b[3], c[3], sum[3], c_out) ;

endmodule



// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps     

module Test_bench;
reg [3:0] a;
reg [3:0] b;
reg      c_in;

wire [3:0] sum;
wire      c_out;

 //module Adder_4bit (input a, b, c_in, output sum, c_out);
Adder_4bit UUT(
.a(a),
.b(b),
.c_in(c_in),
.sum(sum),
.c_out(c_out)
);

initial begin
a  = 4'h0;
b  = 4'h0;
c_in = 4'h0;
$monitor(a,b,c_in,sum,c_out);
#160; c_in = 4'h1;
end

always #20  a = a + 3;
always #40  b = a + 2;


initial begin
      #320 $finish();
end
endmodule