適用於DE2-70 LFSR的偽亂數

適用於DE2-70 LFSR的偽亂數

//==========================
//FPGA產生基於LFSR的偽亂數
//==========================
module LFSR(SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3 ,HEX4 );
 input  [17:0] SW;   // toggle switches
 input  [3:0] KEY;       // Push bottom
 input  CLOCK_50;   //Clock 27MHz , 50Mhz

 output [17:0] LEDR;   // red  LEDS
 output [8:0] LEDG;   // green LEDs
 
 output [6:0] HEX0,HEX1,HEX2,HEX3 ,HEX4; //7-segment display

 //set original program input , output


 //cnt5 (Clk,Clr,Q1,Q2);
 //input  Clk,Clr;  // 一位元輸入
 //output [3:0]  Q1,Q2; // 四位元輸出
 //reg    [3:0]  Q1,Q2; // 宣告為暫存器資料

 wire   Clk ,Clr ;

 wire [7:0] segout0;   //HEX 0
 wire [7:0] segout1;   //HEX 1
 wire [7:0] segout2;   //HEX 2
 wire [7:0] segout3;   //HEX 3

 //assign rest_n=KEY[3];
 //assing clk=CLOCK_50;
 //assign load=KEY[0];
 //assign seed[7:0] =  SW[7:0];
 //assign rand_num[7:0] =  LEDR[7:0];
 wire clk_1hz;

 //clk_div_1hz(clk_in , Reset, clk_out);
 clk_div_1hz u2(CLOCK_50, KEY[3], clk_1hz);

 _7seg UUT0(.hex((LEDR[3:0])),.seg(segout0));
           
 _7seg UUT1(.hex((LEDR[7:4])),.seg(segout1)); 
 assign HEX0=segout0[6:0];
 assign HEX1=segout1[6:0]; 

 RanGen(
    SW[17],    /*rst_n is necessary to prevet locking up*/
    clk_1hz,   /*clock signal*/
    SW[16],    /*load seed to rand_num,active high */
    SW[7:0],   //seed
    LEDR[7:0]          /*random number output*/
  );

endmodule

//=================================

module RanGen(
    input               rst_n,    /*rst_n is necessary to prevet locking up*/
    input               clk,      /*clock signal*/
    input               load,     /*load seed to rand_num,active high */
    input      [7:0]    seed,   
    output reg [7:0]    rand_num  /*random number output*/
);


always@(posedge clk or negedge rst_n)
begin
    if (!rst_n)   //or (!rst_n)
        rand_num    <=8'b0;
    else if(load)
        rand_num <=seed;    /*load the initial value when load is active*/
    else
        begin
            rand_num[0] <= rand_num[7];
            rand_num[1] <= rand_num[0];
            rand_num[2] <= rand_num[1];
            rand_num[3] <= rand_num[2];
            rand_num[4] <= rand_num[3]^rand_num[7];
            rand_num[5] <= rand_num[4]^rand_num[7];
            rand_num[6] <= rand_num[5]^rand_num[7];
            rand_num[7] <= rand_num[6];
        end
           
end

endmodule

module clk_div_1hz(clk_in , Reset, clk_out);
input clk_in ;
input Reset;
output reg  clk_out;

integer i;
always@(posedge clk_in or negedge Reset) begin
 if (!Reset) begin
   i=0;
   clk_out=0;
   end
 else begin
    i= i+1 ;
    if (i>=24_999_999) begin
        clk_out  = ~clk_out;
        i=0;
       end
    end   
end           

endmodule

//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//-----------------------------------------
module _7seg(hex , seg);
    input  [3:0] hex;
    output [7:0] seg;
    reg    [7:0] seg;
       

 // segment encoding
 //      0
 //     ---
 //  5 |   | 1
 //     ---   <- 6
 //  4 |   | 2
 //     ---
 //      3
 always @(hex)
 begin
  case (hex)
       // Dot point is always disable
       4'b0001 : seg = 8'b11111001;   //1 = F9H
       4'b0010 : seg = 8'b10100100;   //2 = A4H
       4'b0011 : seg = 8'b10110000;   //3 = B0H
       4'b0100 : seg = 8'b10011001;   //4 = 99H
       4'b0101 : seg = 8'b10010010;   //5 = 92H
       4'b0110 : seg = 8'b10000010;   //6 = 82H
       4'b0111 : seg = 8'b11111000;   //7 = F8H
       4'b1000 : seg = 8'b10000000;   //8 = 80H
       4'b1001 : seg = 8'b10010000;   //9 = 90H
       4'b1010 : seg = 8'b10001000;   //A = 88H
       4'b1011 : seg = 8'b10000011;   //b = 83H
       4'b1100 : seg = 8'b11000110;   //C = C6H
       4'b1101 : seg = 8'b10100001;   //d = A1H
       4'b1110 : seg = 8'b10000110;   //E = 86H
       4'b1111 : seg = 8'b10001110;   //F = 8EH
       default : seg = 8'b11000000;   //0 = C0H
     endcase
   end

endmodule