Flip-Flop Latch

// File  : D flip flop using behavior modeling style.v

module d_flip_flop ( din ,clk ,reset ,dout );

output dout ;
reg dout ;

input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;

always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else
dout <= din ;
end

endmodule


// File: SR (set reset) Flip Flop using Behavior Modeling Style.v

module sr_flip_flop ( s ,r ,clk ,reset ,q ,qb );

output q ;
reg q ;
output qb ;
reg qb ;

input s ;
wire s ;
input r ;
wire r ;
input clk ;
wire clk ;
input reset ;
wire reset ;

always @ (posedge (clk)) begin
if (reset) begin
q <= 0;
qb <= 1;
end
else begin
if (s!=r) begin
q <= s;
qb <= r;
end
else if (s==1 && r==1) begin
q <= 1'bZ;
qb <= 1'bZ;
end
end
end


endmodule

// File   : JK flip flop using Behavior Modeling Style.v



module JK_flip_flop ( j ,k ,clk ,reset ,q ,qb );

output q ;
reg q ;
output qb ;
reg qb ;

input j ;
wire j ;
input k ;
wire k ;
input clk ;
wire clk ;
input reset ;
wire reset ;

always @ (posedge (clk)) begin
if (reset) begin
q <= 0;
qb <= 1;
end
else begin
if (j!=k) begin
q <= j;
qb <= k;
end
else if (j==1 && k==1) begin
q <= ~q;
qb <= ~qb;
end
end
end


endmodule

// File  : Toggle Flip Flop using Behavior Modeling Style.v


module t_flip_flop ( t ,clk ,reset ,dout );

output dout ;
reg dout ;

input t ;
wire t ;
input clk ;
wire clk ;
input reset ;
wire reset ;

initial dout = 0;

always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else begin
if (t)
dout <= ~dout;
end
end

endmodule

// File        : D Latch using Behavior Modeling Style.v


module D_latch ( enable ,din ,reset ,dout );

output dout ;
reg dout ;

input enable ;
wire enable ;
input din ;
wire din ;
input reset ;
wire reset ;

always @ (enable or din or reset) begin
if (reset)
dout = 0;
else begin
if (enable)
dout = din;
end
end

endmodule

// File     : SR latch using Behavior Modeling Style.v



module SR_Latch ( s ,r ,enable ,reset ,q ,qb );

output q ;
reg q ;
output qb ;
reg qb ;

input s ;
wire s ;
input r ;
wire r ;
input enable ;
wire enable ;
input reset ;
wire reset ;

always @ (enable or s or r or reset) begin
if (reset) begin
q = 0;
qb = 1;
end else if (enable) begin
if (s!=r) begin
q = s;
qb = r;
end else if (s==1 && r==1) begin
q = 1'bZ;
qb = 1'bZ;
end
end
end

endmodule