Counter

• 
  
• Design of 2 Bit Binary Counter.
• Design of 4 Bit Binary Counter.
• Design of MOD-6 Counter.
• Design of Integer Counter.
• Design of BCD Counter or (MOD-10) Counter.
• 
  

// File  : Design of 2 Bit Counter using Behavior Modeling style.v

module counter_2bit ( clk ,reset ,dout );

output [1:0] dout ;
reg [1:0] dout ;

input clk ;
wire clk ;
input reset ;
wire reset ;

initial dout = 0;

always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else
dout <= dout + 1;
end

endmodule


// File   : Design of 4 Bit Counter using Behavior Modeling Style.v


module Counter_4Bit ( clk ,reset ,dout );

output [3:0] dout ;
reg [3:0] dout ;

input clk ;
wire clk ;
input reset ;
wire reset ;

initial dout = 0;

always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else
dout <= dout + 1;
end


endmodule

// File : Design of MOD-6 counter using behavior Modeling Style.v


module counter_mod6 ( clk ,reset ,dout );

output [2:0] dout ;
reg [2:0] dout ;

input clk ;
wire clk ;
input reset ;
wire reset ;

initial dout = 0;

always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else if (dout<5)
dout <= dout + 1;
else
dout <= 0;
end
  
endmodule


// File   : Design of integer counter using Behavior Modeling Style.v


module counter_integer ( clk ,reset ,dout );

output [9:0] dout ;
reg [9:0] dout ;

input clk ;
wire clk ;
input reset ;
wire reset ;

initial dout = 0;

always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else if (dout < 1023)
dout <= dout + 1;
else if (dout==1023)
dout <= 0;
end


endmodule

// File   : Design of BCD Counter using Behavior Modeling Style.v


module BCD_Counter ( clk ,reset ,dout );

output [3:0] dout ;
reg [3:0] dout ;

input clk ;
wire clk ;
input reset ;
wire reset ;

initial dout = 0 ;

always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else if (dout<=9) begin
dout <= dout + 1;
end else if (dout==9) begin
dout <= 0;
end
end


endmodule