Verilog Dataflow 範例

Verilog Dataflow 範例

module ex1(
a,
b,
c,
F,
G
);


input a;
input b;
input c;
output F;
output G;

wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_11;
wire SYNTHESIZED_WIRE_12;
wire SYNTHESIZED_WIRE_6;
wire SYNTHESIZED_WIRE_8;
wire SYNTHESIZED_WIRE_9;
wire SYNTHESIZED_WIRE_10;

assign SYNTHESIZED_WIRE_0 =  ~a;

assign SYNTHESIZED_WIRE_11 =  ~b;

assign SYNTHESIZED_WIRE_8 = ~(a | c);

assign SYNTHESIZED_WIRE_12 =  ~c;

assign SYNTHESIZED_WIRE_6 = SYNTHESIZED_WIRE_0 ^ b;

assign F = SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;

assign SYNTHESIZED_WIRE_10 = c | SYNTHESIZED_WIRE_11;

assign SYNTHESIZED_WIRE_9 = SYNTHESIZED_WIRE_12 | SYNTHESIZED_WIRE_11;

assign SYNTHESIZED_WIRE_2 = SYNTHESIZED_WIRE_6 & SYNTHESIZED_WIRE_12;

assign G = SYNTHESIZED_WIRE_8 & SYNTHESIZED_WIRE_9;

assign SYNTHESIZED_WIRE_1 = ~(SYNTHESIZED_WIRE_10 & b);



endmodule

module ex1( a,b,c,F,G);

input a,b,c;

output F,G;

wire w0,w1,w2;

wire w3,w4,w5,w6;

wire w7,w8;

assign w0= ~a;

assign w1= ~b;

assign w2= ~c;

assign w3= (w0 ^ b) & (w2);

assign w4=  ~(b &  (w1 | c));

assign w4=   ~(a | c);

assign w5=  w1 | w2 ;

assign w7= w3| w4 ;

assign w8= w5 & w6 ;

endmodule

`timescale 100ns/10ps

module Test_bech;

reg a=1'b0;

reg b=1'b0;

reg c=1'b0;

wire F,G;

ex1 UUT (

        .a(a),

        .b(b),

        .c(c),

        .F(F),

        .G(G));

    initial

    begin 

      #800; // Final time:  800 ns

        $stop;

    end

    initial

    begin

        // -----  Current Time:  100ns

        #100;

        a=1'b0; b=1'b0; c=1'b1;  

        // -----  Current Time:  200ns

        #100;

        a=1'b0; b=1'b1; c=1'b0;  

        // -----  Current Time:  300ns

        #100;

        a=1'b0; b=1'b1; c=1'b1;  

        // -----  Current Time:  400ns

        #100;

        a=1'b1; b=1'b0; c=1'b0;  

        // -----  Current Time:  500ns

        #100;

        a=1'b1; b=1'b0; c=1'b1;  

        // -----  Current Time:  600ns

        #100;

        a=1'b1; b=1'b1; c=1'b0;  

        // -----  Current Time:  700ns

        #100;

        a=1'b1; b=1'b1; c=1'b1;  

    end

            

endmodule