Half Adder Behavioral Model using Case Statement in Verilog

Half Adder Behavioral Model using Case Statement in Verilog 

源自於 https://electronicstopper.blogspot.com/2017/06/half-adder-behavioral-model-using-case.html
Code:

module halfadder3(input [1:0]a, output reg sum, carry);

always@(a)
begin

case(a)
2'b00:
 begin
 sum <= 0;
 carry <= 0;
 end
2'b11:
 begin
 sum <= 0;
 carry <= 1;
 end
default:
 begin
 sum <= 1;
 carry <= 0;
 end
endcase

end

endmodule

Testbench Code:

module half_adder_verilog_tb();

reg [1:0]a;
wire sum, carry;

halfadder3 dut (.a(a), .sum(sum), .carry(carry));

initial
begin

a[1] = 1'b0;
a[0] = 1'b0;
#50;

a[1] = 1'b0;
a[0] = 1'b1;
#50;

a[1] = 1'b1;
a[0] = 1'b0;
#50;

a[1] = 1'b1;
a[0] = 1'b1;

end

endmodule

Output: