VHDL Generating the Clock Source (divided 32 5 bits)

VHDL   Generating the Clock Source


---
--
--Outputs
--LED1 <= CLK1; simply routes the source clock (130Hz) to LED 1.
--LED2 <= CLK_DIV(4); routes bit 4 of the CLK_DIV register to LED 2.
--        This is input clock pulse divided by 32.
--
---

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock_divider_top is
    Port ( CLK1    : in  STD_LOGIC;
           Clear   : in  STD_LOGIC;
           LED1    : out STD_LOGIC;
           LED2    : out STD_LOGIC);
end clock_divider_top;

architecture Behavioral of clock_divider_top is
signal CLK_DIV : std_logic_vector (4 downto 0);  
-- routes bit 4 of the CLK_DIV register to LED 2.
-- LED2 <= CLK_DIV(4);   ----div 32
-- signal CLK_DIV : std_logic_vector (9 downto 0);  
-- LED2 <= CLK_DIV(9);   ----div 1024

begin
    -- clock divider
    -- behavioral description of the counter
   process(CLK1, Clear) begin
     if Clear = '0' then
       CLK_DIV <= "00000";
     elsif (CLK1'Event and CLK1 = '1') then
            CLK_DIV <= CLK_DIV + 1 ;
     end if;
   end process;
 
   LED1 <= CLK_DIV(0);
   LED2 <= CLK_DIV(4);
 
end Behavioral ;