//輸出顯示在HEX2~0上，用KEY0 RESET(重置)
//計數器的控制信號由50MHz的時鐘提供。
//當計數值到達 SW[11:8] SW[7:4] SW[3:0] 時計數值回到000
//分析：
//1. 按秒遞增計數，所以要把50MHz的時鐘分頻得到1Hz的脈衝。
//2. 3位元BCD計數器，可用1位元BCD計數器組合，其計數範圍000~999。
//Part I 代碼如下：
//
module BCD_000_999 (CLOCK_50,KEY,HEX2,HEX1,HEX0);
output [6:0]HEX2,HEX1,HEX0; //輸出顯示
input CLOCK_50; //50MHz時鐘
input [0:0]KEY; //復位
wire clk_1hz; //1hz時鐘信號
wire [11:0]cnt; //計數器輸出
reg [11:0]cnt_tmp;
wire e2,e3;
supply1 vdd;
wire [3:0] swa2,swb2,swc2;
BCD_SW_int(SW[11:8],SW[7:4],SW[3:0],swa2,swb2,swc2);
always @(swa2 or swb2 or swc2)
begin
if ((swa2==cnt[11:8]) && (swb2==cnt[7:4]) && (swc2==cnt[3:0]) )
begin
cnt_tmp[11:0]=12'b0;
end
end
assign cnt=cnt_tmp;
assign e2=cnt[3]&cnt[0];
assign e3=e2&(cnt[7]&cnt[4]);
//分頻產生1hz的脈衝
_1HZ u0 (.CLK(CLOCK_50),
.RSTn(KEY),
.HZ_1(clk_1hz));
//3-digit BCD計數器
counter10 u1(.en(vdd),
.clk(clk_1hz),
.rst_n(KEY),
.q(cnt[3:0])
);
counter10 u2(.en(e2),
.clk(clk_1hz),
.rst_n(KEY),
.q(cnt[7:4])
);
counter10 u3(.en(e3),
.clk(clk_1hz),
.rst_n(KEY),
.q(cnt[11:8])
);
//解碼顯示
_7seg h0 (.hex(cnt[3:0]),.seg(HEX0));
_7seg h1 (.hex(cnt[7:4]),.seg(HEX1));
_7seg h2 (.hex(cnt[11:8]),.seg(HEX2));
endmodule
//******************************
module BCD_SW_in(a,b,c,a1,b1,c1);
input [3:0] a,b,c;
output reg [3:0] a1,b1,c1;
always @(a or b or c)
begin
if(a<9)
a1=a;
else
a1=4'b1001;
if(b<9)
b1=b;
else
b1=4'b1001;
if(c<9)
c1=c;
else
c1=4'b1001;
end
endmodule
//******************************
// 50MHZ 變成1HZ
//******************************
module _1HZ (CLK, RSTn, HZ_1);
input CLK;
input RSTn;
output HZ_1;
/*************************************/
parameter T1S = 26'd50_000_000; //50MHZ
/*************************************/
//50_000_000(10)=2FAF080(16) 2+24=26bit
reg [25:0]Count1;
always @ ( posedge CLK or negedge RSTn )
begin
if( !RSTn )
Count1 <= 26'd0;
else if( Count1 == T1S )
Count1 <= 26'd0;
else
Count1 <= Count1 + 1'b1;
end
/*************************************/
reg rLED_Out;
always @ ( posedge CLK or negedge RSTn )
begin
if( !RSTn )
rLED_Out <= 1'b0;
else if( Count1 >= 26'd0 && Count1 < 26'd25_000_000 )
//0.5sec ON , o.5sec OFF
rLED_Out <= 1'b1;
else
rLED_Out <= 1'b0;
end
/***************************************/
assign HZ_1 = rLED_Out;
/***************************************/
endmodule
//除10 verilog 程式
//******************************
module counter10(en,clk,rst_n,q);
output reg [3:0]q;
input en,clk,rst_n;
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
q<=4'b0;
else if(!en)
q<=q;
else if(q==4'b1001)
q<=4'b0;
else
q<=q+1'b1;
end
endmodule
//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//-----------------------------------------
module _7seg(hex , seg);
input [3:0] hex;
output [7:0] seg;
reg [7:0] seg;
//Binary 轉7-segment verilog 程式
//******************************
// segment encoding
// 0
// ---
// 5 | | 1
// --- <- 6
// 4 | | 2
// ---
// 3
always @(hex)
begin
case (hex)
// Dot point is always disable
4'b0001 : seg = 8'b11111001; //1 = F9H
4'b0010 : seg = 8'b10100100; //2 = A4H
4'b0011 : seg = 8'b10110000; //3 = B0H
4'b0100 : seg = 8'b10011001; //4 = 99H
4'b0101 : seg = 8'b10010010; //5 = 92H
4'b0110 : seg = 8'b10000010; //6 = 82H
4'b0111 : seg = 8'b11111000; //7 = F8H
4'b1000 : seg = 8'b10000000; //8 = 80H
4'b1001 : seg = 8'b10010000; //9 = 90H
4'b1010 : seg = 8'b10001000; //A = 88H
4'b1011 : seg = 8'b10000011; //b = 83H
4'b1100 : seg = 8'b11000110; //C = C6H
4'b1101 : seg = 8'b10100001; //d = A1H
4'b1110 : seg = 8'b10000110; //E = 86H
4'b1111 : seg = 8'b10001110; //F = 8EH
default : seg = 8'b11000000; //0 = C0H
endcase
end
endmodule
沒有留言:
張貼留言