計時器, 產生 0:0:0 ~ 23:59:59 計時值

module Timer_24hours (CLOCK_50,KEY,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0);

 output [6:0] HEX5,HEX4,HEX3,HEX2,HEX1,HEX0; //輸出顯示
 input CLOCK_50; //50MHz時鐘
 input [0:0]KEY; //復位

 wire [7:0] H1,M1,S1; 
 timer1 UUT0 (CLOCK_50,KEY[0],H1,M1,S1);  
//Call By in Order
 //module timer1 (Clk50M, Clr, H, M, S);


 //解碼顯示
 hex_7seg h0 (.hex(H1[7:4]),.seg(HEX5));
 hex_7seg h1 (.hex(H1[3:0]),.seg(HEX4));

 hex_7seg h2 (.hex(M1[7:4]),.seg(HEX3));
 hex_7seg h3 (.hex(M1[3:0]),.seg(HEX2));

 hex_7seg h4 (.hex(S1[7:4]),.seg(HEX1));
 hex_7seg h5 (.hex(S1[3:0]),.seg(HEX0));


 endmodule






// Ch10 timer1.v
// 計時器, 產生 0:0:0 ~ 23:59:59 計時值

module timer1 (Clk50M, Clr, H, M, S);
input  Clk50M,Clr; // 一位元輸入
output [7:0] H,M,S; // 八位元輸出

reg    [7:0] H,M,S; // 宣告為暫存器資料
reg    [25:0] Q; // 宣告為暫存器資料
//50_000_000(10)=2FAF080(16) 26bit Data length

reg    Clk1; // 宣告為暫存器資料

// 除頻得 1Hz
always@ (posedge Clk50M)
  begin
    if (!Clr || Q == 49_999_999) // 除 50M
      Q = 0;
    else 
      Q = Q + 1;
    Clk1 = Q[25]; //Clk1=Q[25] 產生一個脈波
  end 


// 產生計時值
always@(posedge Clk1) // 時脈為 1 Hz
  if (!Clr) // 全部歸零
    begin  H = 0;  M = 0;  S = 0;  end
  else if ({H,M,S} == 24'h235959) // 等於 23:59:59
    {H,M,S} = 0;
  else if ({H[3:0],M,S} == 20'h95959) // 等於 X9:59:59
    begin
      H[7:4] = H[7:4] + 1;
      H[3:0] = 0;
      M = 0;  S = 0;
    end
  else if ({M,S} == 16'h5959) // 等於 XX:59:59
    begin
      H[3:0] = H[3:0] + 1;
      M = 0;  S = 0;
    end
  else if ({M[3:0],S} == 12'h959) // 等於 XX:X9:59
    begin
      M[7:4] = M[7:4] + 1;
      M[3:0] = 0;
      S = 0;
    end
  else if (S == 8'h59) // 等於 XX:XX:59
    begin
      M[3:0] = M[3:0] + 1;
      S = 0;
    end
  else if (S[3:0] == 4'h9) // 等於 XX:XX:X9
    begin
      S[7:4] = S[7:4] + 1;
      S[3:0] = 0;
    end
  else
    S[3:0] = S[3:0] + 1;

endmodule


//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//----------------------------------------- 
module hex_7seg(hex , seg);

    input  [3:0] hex;
    output [7:0] seg;
    reg    [7:0] seg;
    
//Binary 轉7-segment  verilog 程式
//******************************
 // segment encoding
 //      0
 //     ---  
 //  5 |   | 1
 //     ---   <- 6
 //  4 |   | 2
 //     ---
 //      3

 always @(hex)
 begin
  case (hex)
       // Dot point is always disable
       4'b0001 : seg = 8'b11111001;   //1 = F9H
       4'b0010 : seg = 8'b10100100;   //2 = A4H
       4'b0011 : seg = 8'b10110000;   //3 = B0H
       4'b0100 : seg = 8'b10011001;   //4 = 99H
       4'b0101 : seg = 8'b10010010;   //5 = 92H
       4'b0110 : seg = 8'b10000010;   //6 = 82H
       4'b0111 : seg = 8'b11111000;   //7 = F8H
       4'b1000 : seg = 8'b10000000;   //8 = 80H
       4'b1001 : seg = 8'b10010000;   //9 = 90H
       4'b1010 : seg = 8'b10001000;   //A = 88H
       4'b1011 : seg = 8'b10000011;   //b = 83H
       4'b1100 : seg = 8'b11000110;   //C = C6H
       4'b1101 : seg = 8'b10100001;   //d = A1H
       4'b1110 : seg = 8'b10000110;   //E = 86H
       4'b1111 : seg = 8'b10001110;   //F = 8EH
       default : seg = 8'b11000000;   //0 = C0H
     endcase
   end
   

endmodule