HDLBits/Building Larger Circuits/FSM: Sequence 1101 recognizer（Exams/review2015 fsmseq）

HDLBits/Building Larger Circuits/FSM: Sequence 1101 recognizer（Exams/review2015 fsmseq）

 This is the second component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.

Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Getting stuck in the final state is intended to model going to other states in a bigger FSM that is not yet implemented. We will be extending this FSM in the next few exercises.

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output reg start_shifting);
    
    parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5;
    reg[2:0] state, next_state;

   always @(posedge clk) begin
        // State flip-flops with asynchronous reset
        if(reset)begin
           state <= s0; 
        end
        else begin
           state <= next_state; 
        end
    end
    always@(*) begin
case (state)
                    s0:    next_state=data?s1:s0;
                    s1:    next_state=data?s2:s0;
                    s2:    next_state=data?s2:s3;
                    s3:    next_state=data?s4:s0;
                    s4:    next_state=data?s2:s0;
                    default:    next_state=s0;
endcase
    end
   always@(posedge clk)
        if(reset)
            start_shifting <= 0;
    else if(next_state==s4) //注意此处的状态是next_state;
            start_shifting <= 1;
endmodule