DE2-115 開發 以 2to4 Decoder 74139 為例

DE2-115 開發 以 2to4 Decoder 74139 為例 

module Decoder_2x4_74139 (SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3,HEX4 ,HEX5 ,HEX6,HEX7, GPIO );
 input  [17:0] SW;   // toggle switches
 input  [7:0] KEY;       // Push bottom
 input  CLOCK_50;   //Clock 27MHz , 50Mhz
 output [17:0] LEDR;   // red  LEDS
 output [8:0] LEDG;   // green LEDs
 output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display
 output [6:0] HEX4,HEX5,HEX6,HEX7; //7-segment display
 inout  [35:0] GPIO;
 assign HEX0=7'b111_1111;
 assign HEX1=7'b111_1111;
 assign HEX2=7'b111_1111;
 assign HEX3=7'b111_1111;
 assign HEX4=7'b111_1111;
 assign HEX5=7'b111_1111;
 assign HEX6=7'b111_1111;
 assign HEX7=7'b111_1111;
 
 //decoder2to4_Structural (xl, x0, e, d);
 decoder2to4_Structural(SW[1],SW[0],SW[2],LEDR[3:0]);
 
 //decoder2to4_Dataflow(in,en,y);
 decoder2to4_Dataflow(SW[5:4],SW[6],LEDR[7:4]);
 
 //decoder2to4_Behavioral (e, i, d) ;
 decoder2to4_Behavioral(SW[10],SW[9:8],LEDR[11:8]);
 
endmodule
//Structural Modeling
// Structural description of a 2-to-4 decoder
module decoder2to4_Structural (xl, x0, e, d);
input xl, x0, e;
output [3:0] d; //output vector d must be declared as wire.
wire [3:0] d; //if vector d is not declared as wire, Verilog
wire xll, x00; //will make vector d one bit by default.
not invl (xl1, xl);
not inv2 (x00, x0);

and andl (d[0], xl1, x00, e);
and and2 (d[1], xl1, x0 , e);
and and3 (d[2], xl , x00, e);
and and4 (d[3], xl , x0 , e);
endmodule 
//Dataflow Modeling 
module decoder2to4_Dataflow(in,en,y);
input [1:0]in;
input en;
output [3:0]y;

assign y[0]= (~in[1]) & (~in[0])  & en;
assign y[1]= (~in[1]) & in[0]     & en;
assign y[2]=    in[1] & (~ in[0]) & en;
assign y[3]=    in[1] & in[0]     & en;
endmodule
//Behavioral Modeling 
module decoder2to4_Behavioral (e, i, d) ;
output [3:0]d;
input  [1:0]i;
input e;
reg [3:0] d;
always @ (i or e)
if (e==1)
begin
case (i)
0: d = 4'b1110;
1: d = 4'b1101;
2: d = 4'b1011;
3: d = 4'b0111;
default d = 4'bxxxx;
endcase
end
else
d = 4'b0000;
endmodule