Verilog for 4bit 2x1 multiplexer

Verilog for 4bit 2x1 multiplexer 

module mux_2to1_4bit(a,b,sel,ena,out);
input [3:0] a,b;
//[3:0] A;         // A為4bit，A[3]，A[2]，A[1]，A[0]
input sel,ena;
output [3:0] out;
reg [3:0] out;
wire ct1,ct0;

assign ct1  = (ena & sel);
assign ct0  = (ena & ~sel);

always @ (a or b or ct1 or ct0)
begin
if (ct1) 
out= a;
if (ct0)
out= b;
if (ena==1'b0)
    out= 4'bzzzz;
end

endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps     
module tb_2to1_mux;

   // Declare internal reg variables to drive design inputs
   // Declare wire signals to collect design output
   // Declare other internal variables used in testbench
   reg [3:0] a;
   reg [3:0] b;
   reg ena ,sel;
 
   wire [3:0] out;
   integer i;

   // Instantiate one of the designs, in this case, we have used the design with case statement
   // Connect testbench variables declared above with those in the design
   mux_2to1_4bit  DUT  (   .a (a),
                           .b (b),
                           .sel (sel),
                           .ena (ena),
                           .out (out));

   // This initial block is the stimulus
   initial begin
      // Launch a monitor in background to display values to log whenever a/b/c/d/sel/out changes
      $monitor ("[%0t] sel=0x%0h a=0x%0h b=0x%0h ena=0x%0h out=0x%0h", $time, sel, a, b, ena, out);

       // 1. At time 0, drive random values to a/b/c/d and keep sel = 0
      ena=1;
      sel <= 0;
      a <= $random;
      b <= $random;
      // 2. Change the value of sel after every 5ns
 
  #5 sel <= 1;
  ena=1;
      a <= $random;
      b <= $random;

      #5  sel <= 0;
      ena=0;
      a <= $random;
      b <= $random;

      #5  sel <= 1;
      ena=0;
      a <= $random;
      b <= $random;

      // 3. After Step2 is over, wait for 5ns and finish simulation
      #5 $finish;
   end
endmodule