UP Down MOD 10 適用於 DE2-70

UP Down MOD10 適用於DE2-70 

//RESET --> KEY[0]
//Enable ==>SW[17]
//UP/DN ==>SW[0]
//Clock ==>KEY[1]
//Output LED[3:0]

//附有致能的上下數計數器
//根據「UP」來做 +1/-1, 附有致能的 mode-10 上下數計數器
// EN='0' , D=「正反器的輸出」所以沒有變化
// EN='1' 且「UP」='1' , D=「+1 電路」輸出會遞增
// EN='1' 且「UP」='0' , D=「-1 電路」輸出會遞減


module up_dn_10(SW,KEY,LEDR, LEDG , CLOCK_50,HEX0 ,HEX1 ,HEX2,HEX3 ,HEX4 );

 input [17:0]SW;
 input [3:0]KEY;
 input CLOCK_50;
 output [17:0]LEDR;
 output [8:0] LEDG;   // green LEDs
 output [6:0] HEX0,HEX1,HEX2,HEX3 ,HEX4; //7-segment display

 wire [7:0] segout0;   //HEX


 EN_UDCNT10 ( .RESET_B(KEY[0]),
     .CLK(KEY[1]),
     .EN(SW[17]),
     .UP(SW[0]),
     .Q(LEDR[3:0])
      );

 _7seg UUT0(.hex(LEDR[3:0]),.seg(segout0));

 assign HEX0 =segout0[6:0];     

endmodule

/* EN_UDCNT10 */
module EN_UDCNT10 ( RESET_B, CLK, EN, UP, Q);
input RESET_B, CLK, EN, UP;
output [3:0] Q;
reg [3:0] Q;

 always @( posedge CLK or negedge RESET_B  )
  if ( !RESET_B )
   Q <= 0;
  else if ( EN )
   if ( UP )   // COUNT UP
    if ( Q == 9 )
     Q <= 0;
    else
     Q <= Q + 1;
   else    // COUNT DOWN
    if ( Q == 0 )
     Q <= 9;
    else
     Q <= Q - 1;           


endmodule

//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//-----------------------------------------
module _7seg(hex , seg);
    input  [3:0] hex;
    output [7:0] seg;
    reg    [7:0] seg;
 
     

 // segment encoding
 //      0
 //     ---
 //  5 |   | 1
 //     ---   <- 6
 //  4 |   | 2
 //     ---
 //      3
 always @(hex)
 begin
  case (hex)
       // Dot point is always disable
       4'b0001 : seg = 8'b11111001;   //1 = F9H
       4'b0010 : seg = 8'b10100100;   //2 = A4H
       4'b0011 : seg = 8'b10110000;   //3 = B0H
       4'b0100 : seg = 8'b10011001;   //4 = 99H
       4'b0101 : seg = 8'b10010010;   //5 = 92H
       4'b0110 : seg = 8'b10000010;   //6 = 82H
       4'b0111 : seg = 8'b11111000;   //7 = F8H
       4'b1000 : seg = 8'b10000000;   //8 = 80H
       4'b1001 : seg = 8'b10010000;   //9 = 90H
       4'b1010 : seg = 8'b10001000;   //A = 88H
       4'b1011 : seg = 8'b10000011;   //b = 83H
       4'b1100 : seg = 8'b11000110;   //C = C6H
       4'b1101 : seg = 8'b10100001;   //d = A1H
       4'b1110 : seg = 8'b10000110;   //E = 86H
       4'b1111 : seg = 8'b10001110;   //F = 8EH
       default : seg = 8'b11000000;   //0 = C0H
     endcase
   end

endmodule